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features ? programmable audio output for interfacing with common audio dac ? pcm format compatible ?i 2 s format compatible ? 8-bit mcu c51 core-based (f max = 20 mhz) ? 2304 bytes of internal ram ? 64k bytes of code memory ? at89c5132: flash (100k write/erase cycles) ? 4k bytes of boot flash memory (at89c5132) ? isp: download from usb (s tandard) or uart (option) ? usb rev 1.1 device controller ? ?full speed? data transmission ? built-in pll ? multimedia card ? interface compatibility ? atmel dataflash ? spi interface compatibility ? ide/atapi interface ? 2 channels 10-bit adc, 8 khz (8 true bits) ? battery voltage monitoring ? voice recording controlled by software ? up to 44 bits of general-purpose i/os ? 4-bit interrupt keyboard port for a 4 x n matrix ? smartmedia ? software interface ? two standard 16-bit timers/counters ? hardware watchdog timer ? standard full duplex uart with baud rate generator ? two wire master and slave modes controller ? spi master and slave modes controller ? power management ? power-on reset ? software programmable mcu clock ? idle mode, power-down mode ? operating conditions ?3v, 10%, 25 ma typical operating at 25c ? temperature range: -40 c to +85 c ? packages ? tqfp80, plcc84 (development board only) ?dice 1. description the at89c5132 is a mass storage device controlling data exchange between various flash modules, hdd and cd-rom. the at89c5132 includes 64k bytes of flash memory and allows in-system program - ming through an embedded 4k bytes of boot flash memory. the at89c5132 include 2304 bytes of ram memory. the at89c5132 provides all the necessary features for man-machine interface including, timers, keyboard port, serial or parallel interface (usb, spi, ide), adc input, i 2 s output, and all external memory interface (nand or nor flash, smartme - dia, multimedia, dataflash cards). 2. typical applications ? flash recorder/writer ? pda, camera, mobile phone ? pc add-on usb microcontroller with 64k bytes flash memory at89c5132 preliminary 4173d?usb?02/06
2 4173d?usb?02/06 at89c5132 3. block diagram figure 3-1. at89c5132 block diagram notes: 1. alternate function of port 3 2. alternate function of port 4 3. alternate function of port 1 8-bit internal bus clock and pll unit c51 (x2 core) ram 2304 bytes flash interrupt handler unit filt x2 x1 mmc interface i/o mdat p0 - p5 10-bit a-to-d converter v ss v dd keyboard interface kin3:0 i 2 s/pcm audio interface avss av dd ain1:0 ports int0 int1 mosi miso timers 0/1 t1 t0 spi/dataflash controller mclk mcmd sck rst aref dsel dclk sclk dout 64k bytes usb controller d+ d- uart rxd txd ide interface ss watchdog flash boot 4k bytes uvss uv dd and brg 11 11 1 1 2222 3 twi controller scl sda 11
3 4173d?usb?02/06 at89c5132 4. pin description figure 4-1. at89c5132 80-pin tqfp package p0.3/ad3 p0.4/ad4 p0.5/ad5 vss vdd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.0/rxd 1 2 3 4 5 6 7 8 13 11 10 p2.2/a10 p2.3/a11 p2.4/a12 p2.6/a14 p2.5/a13 p2.7/a15 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p0.0/ad0 pvss vss x2 x1 tst vss 9 12 14 15 16 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss vdd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss avdd p3.7/rd p3.6/wr p3.5/t1 vdd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt pvdd vdd p1.6/scl 17 18 19 20 21 22 23 24 25 26 27 28 33 31 30 29 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 53 51 50 49 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 73 71 70 69 72 74 75 76 77 78 79 80 ale isp uvdd uvss p5.0 p5.1 p4.7 p4.6 d- d+ p5.3 p5.2 vss vdd p4.5 p4.4 tqfp80
4 4173d?usb?02/06 at89c5132 figure 4-2. at89c5132 84-pin plcc (1) note: 1. for development board only. 4.1 signals all the at89c5132 signals are detailed by functionality in table 1 to table 14 . table 1. ports signal description plcc84 p0.3/ad3 p0.4/ad4 p0.5/ad5 vss vdd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.2/int0 65 64 63 62 61 60 59 58 55 56 57 12 13 14 15 16 17 22 20 19 33 34 35 36 37 4 3 2 1 84 83 82 81 80 79 78 nc p2.3/a11 p2.4/a12 p2.6/a14 p2.5/a13 p2.7/a15 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p5.0 pavss vss x2 nc x1 p3.1/txd 18 21 23 24 25 38 39 40 41 42 69 68 67 66 70 5 6 7 8 9 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss vdd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss avdd vss vdd p3.7/rd p3.0/rxd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt pavdd vdd p1.6/scl 26 43 tst p5.2 p0.0/ad0 77 p2.2/a10 54 ale isp nc p5.1 p4.7 p4.6 76 75 10 11 28 27 29 30 31 32 uvdd uvss 44 45 46 47 48 49 50 51 52 53 74 73 72 71 p4.4 p4.5 vdd vss d- d+ nc p5.3 signal name type description alternate function p0.7:0 i/o port 0 p0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high im pedance inputs. to avoid any parasitic current consumption, floating p0 inputs must be polarized to v dd or v ss . ad7:0 p1.7:0 i/o port 1 p1 is an 8-bit bidirectional i/o port with internal pull-ups. kin3:0 scl sda
5 4173d?usb?02/06 at89c5132 table 2. clock signal description table 3. timer 0 and timer 1 signal description p2.7:0 i/o port 2 p2 is an 8-bit bidirectional i/o port with internal pull-ups. a15:8 p3.7:0 i/o port 3 p3 is an 8-bit bidirectional i/o port with internal pull-ups. rxd txd int0 int1 t0 t1 wr rd p4.7:0 i/o port 4 p4 is an 8-bit bidirectional i/o port with internal pull-ups. miso mosi sck ss p5.3:0 i/o port 5 p5 is a 4-bit bidirectional i/o port with internal pull-ups. - signal name type description alternate function x1 i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/res onator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. x1 is the clock source for internal timing. - x2 o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/res onator circuit is connected to this pin. if an external oscillator is used, leave x2 unconnected. - filt i pll low pass filter input filt receives the rc network of the pll low pass filter. - signal name type description alternate function int0 i timer 0 gate input int0 serves as external run control for timer 0, when selected by gate0 bit in tcon register. external interrupt 0 int0 input sets ie0 in the tcon register. if bit it0 in this register is set, bit ie0 is set by a falling edge on int0 . if bit it0 is cleared, bit ie0 is set by a low level on int0 . p3.2 int1 i timer 1 gate input int1 serves as external run control for timer 1, when selected by gate1 bit in tcon register. external interrupt 1 int1 input sets ie1 in the tcon register. if bit it1 in this register is set, bit ie1 is set by a falling edge on int1 . if bit it1 is cleared, bit ie1 is set by a low level on int1 . p3.3 signal name type description alternate function
6 4173d?usb?02/06 at89c5132 table 4. audio interface signal description table 5. usb controller signal description table 6. mutimediacard interface signal description t0 i timer 0 external clock input when timer 0 operates as a counter, a falling edge on the t0 pin increments the count. p3.4 t1 i timer 1 external clock input when timer 1 operates as a counter, a falling edge on the t1 pin increments the count. p3.5 signal name type description alternate function dclk o dac data bit clock - dout o dac audio data - dsel o dac channel select signal dsel is the sample rate clock output. - sclk o dac system clock sclk is the oversampling clock synchr onized to the digital audio data (dout) and the channel selection signal (dsel). - signal name type description alternate function d+ i/o usb positive data upstream port this pin requires an external 1.5 k pull-up to v dd for full speed operation. - d- i/o usb negative data upstream port - signal name type description alternate function mclk o mmc clock output data or command clock transfer. - mcmd i/o mmc command line bidirectional command channel used for card initialization and data transfer commands. to avoid any parasitic current consumption, unused mcmd input must be polarized to v dd or v ss . - mdat i/o mmc data line bidirectional data channel. to avoid any parasitic current consumption, unused mdat input must be polarized to v dd or v ss . - signal name type description alternate function
7 4173d?usb?02/06 at89c5132 table 7. uart signal description table 8. spi controller signal description table 9. twi controller signal description table 10. a/d converter signal description signal name type description alternate function rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2 and 3. p3.0 txd o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 signal name type description alternate function miso i/o spi master input slave output data line when in master mode, miso receives data from the slave peripheral. when in slave mode, miso outputs data to the master controller. p4.0 mosi i/o spi master output slave input data line when in master mode, mosi outputs data to the slave peripheral. when in slave mode, mosi receives data from the master controller. p4.1 sck i/o spi clock line when in master mode, sck outputs clock to the slave peripheral. when in slave mode, sck receives clock from the master controller. p4.2 ss i spi slave select line when in controlled slave mode, ss enables the slave mode. p4.3 signal name type description alternate function scl i/o twi serial clock when twi controller is in master mode, scl outputs the serial clock to the slave peripherals. when twi controller is in slave mode, scl receives clock from the master controller. p1.6 sda i/o twi serial data sda is the bidirectional two wire data line. p1.7 signal name type description alternate function ain1:0 i a/d converter analog inputs - arefp i analog positive voltage reference input - arefn i analog negative voltage reference input this pin is internally connected to avss. -
8 4173d?usb?02/06 at89c5132 table 11. keypad interface signal description table 12. external access signal description table 13. system signal description signal name type description alternate function kin3:0 i keypad input lines holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. p1.3:0 signal name type description alternate function a15:8 i/o address lines upper address lines for the external bus. multiplexed higher address and data lines for the ide interface. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address and data lines for the external memory or the ide interface. p0.7:0 ale o address latch enable output ale signals the start of an external bus cycle and indicates that valid address information is available on lines a7:0. an external latch is used to demultiplex the address from address/data bus. - isp i/o isp enable input this signal must be held to gnd through a pull-down resistor at the falling reset to force execution of the internal bootloader. - rd o read signal read signal asserted during external data memory read operation. p3.7 wr o write signal write signal asserted during external data memory write operation. p3.6 signal name type description alternate function rst i reset input holding this pin high for 64 oscillator per iods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal pull-down resist or which allows the device to be reset by connecting a capacitor between this pin and v dd . asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. - tst i test input test mode entry signal. this pin must be set to v dd . -
9 4173d?usb?02/06 at89c5132 table 14. power signal description signal name type description alternate function vdd pwr digital supply voltage connect these pins to +3v supply voltage. - vss gnd circuit ground connect these pins to ground. - avdd pwr analog supply voltage connect this pin to +3v supply voltage. - avss gnd analog ground connect this pin to ground. - pvdd pwr pll supply voltage connect this pin to +3v supply voltage. - pvss gnd pll circuit ground connect this pin to ground. - uvdd pwr usb supply voltage connect this pin to +3v supply voltage. - uvss gnd usb ground connect this pin to ground. -
10 4173d?usb?02/06 at89c5132 4.2 internal pin structure table 15. detailed internal pin structure notes: 1. for information on resist ors value, input/output levels, a nd drive capability, refer to the section ?dc characteristics?, page 183 . 2. when the two wire controller is enabled, p 1 , p 2 , and p 3 transistors are disabled allowing pseudo open-drain structure. 3. in port 2, p 1 transistor is continuously driven when ou tputting a high level bit address (a15:8). circuit (1) type pins input tst input/output rst input/output p1 (2) p2 (3) p3 p4 p53:0 input/output p0 mcmd mdat isp psen output ale sclk dclk dout dsel mclk input/output d+ d- r tst vdd r rst vss p vdd watchdog output p 3 vss n p 1 vdd vdd 2 osc latch output periods p 2 vdd vss n p vdd vss n p vdd d+ d-
11 4173d?usb?02/06 at89c5132 5. address spaces the at8xc5132 derivatives implement four different address spaces: ? program/code memory ? boot memory ? data memory ? special function registers (sfrs) 5.0.1 code memory the at89c5132 implements 64k bytes of on-chi p program/code memory in flash technology. the flash memory increases rom functionality by enabling in-circuit electrical erasure and pro - gramming. thanks to the internal charge pump, the high voltage needed for programming or erasing flash cells is generat ed on-chip using the standard v dd voltage. thus, the at89c5132 can be programmed using only one voltage and allows in application software programming commonly known as iap. hardware programming m ode is also available using specific pro - gramming tools. 5.0.2 boot memory the at89c5132 implements 4k bytes of on-chip boot memory provided in flash technology. this boot memory is delivered programmed with a standard bootloader software allowing in sys - tem programming commonly known as isp. it al so contains some a pplication programming interfaces routines commonly known as api allowing user to develop his own bootloader. 5.0.3 data memory the at89c5132 derivatives implement 2304 bytes of on-chip data ram. this memory is divided in two separate areas: ? 256 bytes of on-chip ram memory (standard c51 memory). ? 2048 bytes of on-chip expanded ram memory (eram accessible via movx instructions).
12 4173d?usb?02/06 at89c5132 6. clock controller the at89c5132 clock controller is based on an on-chip oscillator feeding an on-chip phase lock loop (pll). all internal clocks to the peripherals and cp u core are generated by this controller. 6.1 oscillator the at89c5132 x1 and x2 pins are the input and t he output of a single-stage on-chip inverter (see figure 6-1 ) that can be configured with off-chip components such as a pierce oscillator (see figure 6-2 ). value of capacitors and crystal charac teristics are detailed in the section ?dc characteristics?. the oscillator outputs thre e different clocks: a clo ck for the pll, a clock for the cpu core, and a clock for the peripherals as shown in figure 6-1 . these clocks are either enabled or disabled, depending on the power reduction mode as detailed in the section ?power management? on page 44 . the peripheral clock is used to generate the timer 0, timer 1, mmc, adc, spi, and port sampling clocks. figure 6-1. oscillator block diagram and symbol figure 6-2. crystal connection 6.2 x2 feature unlike standard c51 products that require 12 o scillator clock periods per machine cycle, the at89c5132 needs only 6 oscillato r clock periods per machine cycle. this feature called the ?x2 feature? can be enabled using the x2 bit (1) in ckcon (see table 1 ) and allows the at89c5132 to operate in 6 or 12 oscillator clock periods per machine cycle. as shown in figure 6-1 , both cpu and peripheral clocks are affected by this feature. figure 6-3 shows the x2 mode switching waveforms. after reset, the stan dard mode is activated. in st andard mode, the cpu and periph - x1 x2 pd pcon.1 idl pcon.0 peripheral cpu core 0 1 x2 ckcon.0 2 per clock clock clock peripheral clock symbol cpu clock cpu core clock symbol osc clock oscillator clock symbol oscillator clock v ss x1 x2 q c1 c2
13 4173d?usb?02/06 at89c5132 eral clock frequency is the oscilla tor frequency divi ded by 2 while in x2 mode, it is the oscillator frequency. note: 1. the x2 bit reset value depends on the x2b bit in the hardware security byte (see table 12 on page 24 ). using the at89c5132 (flash version) the system can boot either in standard or x2 mode depending on the x2b value. using at 83c51snd1c (rom version) the system always boots in standard mode. x2b bit can be changed to x2 mode later by software. figure 6-3. mode switching waveforms note: in order to prevent any incorrect operation wh ile operating in x2 mode, the user must be aware that all peripherals using clock frequency as time reference (timers?) will have their time refer - ence divided by two. for example, a free runni ng timer generating an interrupt every 20 ms will then generate an inte rrupt every 10 ms. 6.3 pll 6.3.1 pll description the at89c5132 pll is used to generate internal high frequency clock (the pll clock) synchro - nized with an external low-frequency (the oscillator clock). the pll clock provides the audio interface, and the usb interface clocks. figure 6-4 shows the internal structure of the pll. the pfld block is the phase frequency comparat or and lock detector. this block makes the comparison between the reference clock coming from the n divider and the reverse clock com - ing from the r divider and generates some pulses on the up or down signal depending on the edge position of the reverse clock. the pllen bi t in pllcon register is used to enable the clock generation. when the pll is locked, the bit plock in pllcon register (see table 3 ) is set. the chp block is the charge pump that generat es the voltage reference for the vco by inject - ing or extracting charges from the extern al filter connected on pfilt pin (see figure 6-5 ). value of the filter components are detailed in the section ?dc characteristics?. the vco block is the volt age controlled osc illator controlled by the voltage v ref produced by the charge pump. it generates a square wave signal: the pll clock. x1 2 x1 clock x2 bi t x2 mode (1) std mode std mode
14 4173d?usb?02/06 at89c5132 figure 6-4. pll block diagram and symbol figure 6-5. pll filter connection 6.3.2 pll programming the pll is programmed us ing the flow shown in figure 6-6 . as soon as clock generation is enabled, the user must wait until the lock indicato r is set to ensure the clock output is stable. the pll clock frequency will depend on th e audio interface clock frequencies. figure 6-6. pll programming flow 6.4 registers table 1. ckcon register pllen pllcon.1 n6:0 n divider r divider vco pllclk oscclk r 1 + () n1 + ---------------------------------------------- - = osc clock pfld plock pllcon.0 pfilt chp vref up down r9:0 pll clock pll clock symbol pll clock v ss pfilt r c1 c2 v ss pll programming configure dividers n6:0 = xxxxxxb r9:0 = xxxxxxxxxxb enable pll pllres = 0 pllen = 1 pll locked? plock = 1?
15 4173d?usb?02/06 at89c5132 ckcon (s:8fh) ? clock control register reset value = 0000 000xb table 2. pllndiv register pllndiv (s:eeh) ? pll n divider register reset value = 0000 0000b 76543210 twix2 wdx2 - six2 - t1x2 t0x2 x2 bit number bit mnemonic description 7twix2 two-wire clock control bit set to select the oscillat or clock divided by 2 as twi clock input (x2 independent). clear to select the peripheral cl ock as twi clock input (x2 dependent). 6wdx2 watchdog clock control bit set to select the oscillat or clock divided by 2 as wa tchdog clock input (x2 independent). clear to select the peripheral cloc k as watchdog clock input (x2 dependent). 5- reserved the value read from this bit is indeterminate. do not set this bit. 4six2 enhanced uart clock (mode 0 and 2) control bit set to select the oscillat or clock divided by 2 as ua rt clock input (x2 independent). clear to select the peripheral cloc k as uart clock input (x2 dependent).. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2t1x2 timer 1 clock control bit set to select the oscillator clock divided by two as timer 1 clock input (x2 independent). clear to select the peripheral cloc k as timer 1 clock input (x2 dependent). 1t0x2 timer 0 clock control bit set to select the oscillator clock divided by two as timer 0 clock input (x2 independent). clear to select the peripheral cloc k as timer 0 clock input (x2 dependent). 0x2 system clock control bit clear to select 12 clock periods per machine cycle (std mode, f cpu = f per = f osc / 2). set to select 6 clock periods per machine cycle (x2 mode, f cpu = f per = f osc ). 76543210 - n6n5n4n3n2n1n0 bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6-0 n6:0 pll n divider 7-bit n divider.
16 4173d?usb?02/06 at89c5132 table 3. pllcon register pllcon (s:e9h) ? pll control register reset value = 0000 1000b table 4. pllrdiv register pllrdiv (s:efh) ? pll r divider register reset value = 0000 0000b 76543210 r1 r0 - - pllres - pllen plock bit number bit mnemonic description 7 - 6 r1:0 pll least significant bits r divider 2 lsb of the 10-bit r divider. 5 - 4 - reserved the values read from these bits are always 0. do not set these bits. 3pllres pll reset bit set this bit to reset the pll. clear this bit to free the pll and allow enabling. 2- reserved the values read from this bit is always 0. do not set this bit. 1 pllen pll enable bit set to enable the pll. clear to disable the pll. 0plock pll lock indicator set by hardware when pll is locked. clear by hardware when pll is unlocked. 76543210 r9 r8 r7 r6 r5 r4 r3 r2 bit number bit mnemonic description 7 - 0 r9:2 pll most significant bits r divider 8 msb of the 10-bit r divider.
17 4173d?usb?02/06 at89c5132 7. program/code memory the at89c5132 implements 64k bytes of on-chip program/code memory. figure 7-1 shows the split of internal and external program/cod e memory spaces depending on the product. the flash memory increases eprom and rom functi onality by in-circuit electrical erasure and programming. the high voltage needed for programming or erasing flash cells is generated on- chip using the standard v dd voltage, made possible by the in ternal charge pump. thus, the at89c5132 can be programmed using only one volt age and allows in application software pro - gramming. hardware programming mode is also available using common programming tools. see the application note ?programming t89c51x and at89c51x with device programmers?. the at89c5132 implements an additional 4k bytes of on-chip boot flash memory provided in flash memory. this boot memory is delivered programmed with a standard bootloader software allowing in-system programming (isp). it also c ontains some application programming inter - faces (api), allowing in application programming (iap) by using user?s own bootloader. figure 7-1. program/code memory organization 7.1 flash memory architecture as shown in figure 7-2 the at89c5132 flash memory is composed of four spaces detailed in the following paragraphs. figure 7-2. at89c5132 memory architecture 4k bytes boot flash ffffh f000h 0000h 64k bytes code flash ffffh f000h ffffh 64k bytes flash memory 0000h hardware security user 4k bytes flash memory ffffh f000h boot extra row
18 4173d?usb?02/06 at89c5132 7.1.1 user space this space is composed of a 64k bytes flash me mory organized in 512 pages of 128 bytes. it contains the user?s application code. this spac e can be read or written by both software and hardware modes. 7.1.2 boot space this space is composed of a 4k bytes flash me mory. it contains the bootloader for in-system programming and the routines for in-system application programming. this space can only be read or written by hardware mode using a parallel programming tool. 7.1.3 hardware security space this space is composed of one byte: the hardware security byte (hsb see table 7 ) divided in two separate nibbles see table 7 . the msn contains the x2 mode configuration bit and the boot loader jump bit as detailed in section ?boot memory execution? and can be written by software while the lsn contains the lock system level to protect the memory content against piracy as detailed in section ?hardware security system? and can only be written by hardware. 7.1.4 extra row space this space is composed of two bytes: ? the software boot vector (sbv see ta b l e 8 ). this byte is used by the software bootloader to build the boot address. ? the software security byte (ssb see figure ). this byte is used to lock the ex ecution of some bootloader commands. 7.2 hardware security system the at89c5132 implements three lock bits lb2:0 in the lsn of hsb (see table 7 ) providing three levels of security for user?s program as described in table 7 while the at83c51snd1c is always set in read disabled mode. ? level 0 is the level of an erased part and does not enable any security feature. ? level 1 locks the hardware programming of both user and boot memories. ? level 2 locks hardware verifying of both user and boot memories. ? level 3 locks the external execution. notes: 1. u means unprogrammed, p means programmed and x means don?t care (programmed or unprogrammed). 2. lb2 is not implemented in the at89c5132 products. 3. at89c5132 products are delivered with third level programmed to ensur e that the code pro - grammed by software using isp or user?s boot loader is secured from any hardware piracy. table 5. lock bit features (1) level lb2 (2) lb1 lb0 internal execution external execution hardware verifying hardware programming software programming 0 u u u enable enable enable enable enable 1 u u p enable enable enable disable enable 2 u p x enable enable disable disable enable 3 (3) p x x enable disable disable disable enable
19 4173d?usb?02/06 at89c5132 7.3 boot memory execution as internal c51 code space is limited to 64k bytes, some mech anisms are implemented to allow boot memory to be mapped in the code space for execution at addresses from f000h to ffffh. the boot memory is enabled by setting the enboot bit in auxr1 (see table 6 ). the three ways to set this bit are detail ed in the following sections. 7.3.1 software boot mapping the software way to set enboot consists in wr iting to auxr1 from the user?s software. this enables bootloader or api routines execution. 7.3.2 hardware condition boot mapping the hardware condition is based on the isp pin. when driving this pin to low level, the chip reset sets enboot and forces the reset vector to f000h instead of 0000h in order to execute the bootloader software. as shown in figure 7-3 , the hardware condi tion always allows in-system recovery when user?s memory has been corrupted. 7.3.3 programmed condition boot mapping the programmed condition is based on the bootloader jump bit (bljb) in hsb. as shown in figure 7-3 , when this bit is programmed (by hardware or software programming mode), the chip resets enboot and forces the reset vector to f000h instead of 0000h, in order to execute the bootloader software. figure 7-3. hardware boot process algorithm the software process (bootloader) is detaile d in the at89c5132 bootloader datasheet. atmel?s boot loader hardware software hard cond? isp = l? reset hard cond init enboot = 1 pc = f000h fcon = 00h prog cond? bljb = p? standard init enboot = 0 pc = 0000h fcon = f0h prog cond init enboot = 1 pc = f000h fcon = f0h user?s application process process
20 4173d?usb?02/06 at89c5132 7.3.4 preventing flash corruption see ?reset recommendation to prevent flash corruption? on page 45 . 7.4 registers table 6. auxr1 register auxr1 (s:a2h) ? auxiliary register 1 reset value = xxxx 00x0b 7.5 hardware bytes table 7. hsb byte ? hardwa re security byte 76543210 - - enboot - gf3 0 - dps bit number bit mnemonic description 7 - 6 - reserved the values read from these bits are indeterminate. do not set these bits. 5enboot enable boot flash set this bit to map the boot flash in the code space between at addresses f000h to ffffh. clear this bit to disable boot flash. 4- reserved the values read from this bit is indeterminate. do not set this bit. 3gf3 general flag this bit is a general-purpose user flag. 20 always zero this bit is stuck to logic 0 to allow inc auxr1 instruction without affecting gf3 flag. 1- reserved for data pointer extension. 0dps data pointer select bit set to select second data pointer: dptr1. clear to select first data pointer: dptr0. 76543210 x2b bljb - - - lb2 lb1 lb0 bit number bit mnemonic description 7x2b (1) x2 bit program this bit to start in x2 mode. unprogram (erase) this bit to start in standard mode. 6bljb (2) boot loader jump bit program this bit to execute the boot loader at address f000h on next reset. unprogram (erase) this bit to execute user ?s application at address 0000h on next reset. 5 - 4 - reserved the value read from these bits is always unprogrammed. do not program these bits. 3- reserved the value read from this bit is always unprogrammed. do not program this bit.
21 4173d?usb?02/06 at89c5132 reset value = xxuu uxxx, uuuu uuuu after an hardware full chip erase. note: 1. x2b initializes the x2 bit in ckcon during the reset phase. 2. in order to ensure boot loader activation at first power-up, at89c5132 products are delivered with bljb programmed. 3. bits 0 to 3 (lsn) can only be programmed by hardware mode. table 8. sbv byte ? software boot vector reset value = xxxx xxxx, uuuu uuuu after an hardware full chip erase. table 9. ssb byte ? software security byte reset value = xxxx xxxx, uuuu uuuu after an hardware full chip erase. 2 - 0 lb2:0 hardware lock bits refer to for bits description. 76543210 add15 add14 add13 add12 add11 add10 add9 add8 bit number bit mnemonic description 7 - 0 add15:8 msb of the user?s bootloader 16-bit address location refer to the bootloader datasheet for usage information (bootloader dependent). 76543210 ssb7 ssb6 ssb5 ssb4 ssb3 ssb2 ssb1 ssb0 bit number bit mnemonic description 7 - 0 ssb7:0 software security byte data refer to the bootloader datasheet for usage information (bootloader dependent). bit number bit mnemonic description
22 4173d?usb?02/06 at89c5132 8. data memory the at89c5132 provides data memory access in two different spaces: 1. the internal space mapped in three separate segments: ? the lower 128 bytes ram segment ? the upper 128 bytes ram segment ? the expanded 2048 bytes ram segment 2. the external space. a fourth internal segment is available but ded icated to special func tion registers, sfrs, (addresses 80h to ffh ) accessible by direct addressing mode. for information on this segment, refer to the section ?special function registers?, page 29 . figure 8-1 shows the internal and external data memory spaces organization. figure 8-1. internal and external data memory organization 8.1 internal space 8.1.1 lower 128 bytes ram the lower 128 bytes of ram (see figure 8-2 ) are accessible from address 00h to 7fh using direct or indirect addressing modes. the lowest 32 bytes are grouped into 4 banks of 8 registers (r0 to r7). two bits rs0 and rs1 in psw register (see table 13 ) select which bank is in use according to table 10 . this allows more efficient use of c ode space, since register instructions are shorter than instructions that use direct addr essing, and can be used for context switching in interrupt service routines. table 10. register bank selection 2k bytes upper 128 bytes internal ram lower 128 bytes internal ram special function registers 80h 80h 00h 7ffh ffh 00h ffh 64k bytes external xram 0000h ffffh direct addressing addressing 0800h 7fh internal eram direct or indirect indirect addressing extram = 0 extram = 1 rs1 rs0 description 0 0 register bank 0 from 00h to 07h 0 1 register bank 1 from 08h to 0fh 1 0 register bank 2 from 10h to 17h 1 1 register bank 3 from 18h to 1fh
23 4173d?usb?02/06 at89c5132 the next 16 bytes above the register banks form a block of bit-addressable memory space. the c51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h to 7fh. figure 8-2. lower 128 bytes internal ram organization 8.1.2 upper 128 bytes ram the upper 128 bytes of ram are accessible from address 80h to ffh using only indirect addressing mode. 8.1.3 expanded ram the on-chip 2k bytes of expanded ram (eram) are accessible from address 0000h to 07ffh using indirect addressing mode through movx in structions. in this address range, extram bit in auxr register (see table 14 ) is used to select the eram (d efault) or the xram. as shown in figure 8-1 when extram = 0, the eram is sele cted and when extram = 1, the xram is selected, see ?external space? on page 23. the eram memory can be resized using xrs1:0 bi ts in auxr register to dynamically increase external access to the xram space. table 11 details the selected eram size and address range. table 11. eram size selection note: lower 128 bytes ram, upper 128 bytes ram, and expanded ram are made of volatile memory cells. this means that the ram content is indet erminate after power-up and must then be initial - ized properly. 8.2 external space 8.2.1 memory interface the external memory interface comprises the extern al bus (port 0 and port 2) as well as the bus control signals ( rd , wr , and ale). bit-addressable space 4 banks of 8 registers r0 - r7 30h 7fh (bit addresses 0 - 7fh) 20h 2fh 18h 1fh 10h 17h 08h 0fh 00h 07h xrs1 xrs0 eram size address 0 0 256 bytes 0 to 00ffh 0 1 512 bytes 0 to 01ffh 1 0 1k byte 0 to 03ffh 1 1 2k bytes 0 to 07ffh
24 4173d?usb?02/06 at89c5132 figure 8-3 shows the structure of the external address bus. p0 carries address a7:0 while p2 carries address a15:8. data d7:0 is multiplexed with a7:0 on p0. table 12 describes the exter - nal memory interface signals. figure 8-3. external data memory interface structure table 12. external data memory interface signals 8.2.2 page access mode the at89c5132 implement a feature called page access that disables the output of dph on p2 when executing movx @dptr instruction. page a ccess is enable by setting the dphdis bit in auxr register. page access is useful when application uses bo th eram and 256 bytes of xram. in this case, software modifies intensively extram bit to select access to eram or xr am and must save it if used in interrupt service routine. page a ccess allows external access above 00ffh address without generating dph on p2. thus eram is accessed using movx @ri or movx @dptr with dptr < 0100h, < 0200h, < 0400h or < 0800h depending on the xrs1:0 bits value. then xram is accessed using movx @dptr with dptr 0800h regardless of xrs1:0 bits value while keeping p2 for general i/o usage. 8.2.3 external bus cycles this section describes the bus cycles that at89c513 2 executes to read (see figure 8-4 ), and write data (see figure 8-5 ) in the external data memory. signal name type description alternate function a15:8 o address lines upper address lines for the external bus. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address lines and data for the external memory. p0.7:0 ale o address latch enable ale signals indicates that valid address information are available on lines ad7:0. - rd o read read signal output to external data memory. p3.7 wr o write write signal output to external memory. p3.6 ram peripheral at89c5132 p2 p0 ad7:0 a15:8 a7:0 a15:8 d7:0 a7:0 ale wr oe rd wr latch
25 4173d?usb?02/06 at89c5132 external memory cycle takes 6 cpu clock periods. this is equivalent to 12 oscillator clock peri - ods in standard mode or 6 oscillat or clock periods in x2 mode. for further information on x2 mode, refer to the section ?x2 feature?, page 12 . slow peripherals can be accessed by stretching t he read and write cycles. this is done using the m0 bit in auxr register. setting this bit changes the width of the rd and wr signals from 3 to 15 cpu clock periods. for simplicity, the accompanying figures depict the bus cycle wa veforms in idealized form and do not provide precise timing information. for bus cycle timing parameters refer to the section ?ac characteristics?. figure 8-4. external data read waveforms notes: 1. rd signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. 3. when executing movx @dptr instruction, if dphdis is set (page a ccess mode), p2 out - puts sfr content instead of dph. figure 8-5. external data write waveforms notes: 1. wr signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. 3. when executing movx @dptr instruction, if dphdis is set (page a ccess mode), p2 out - puts sfr content instead of dph. ale p0 p2 rd (1) dpl or ri d7:0 dph or p2 (2),(3) p2 cpu clock ale p0 p2 wr (1) dpl or ri d7:0 p2 cpu clock dph or p2 (2),(3)
26 4173d?usb?02/06 at89c5132 8.3 dual data pointer 8.3.1 description the at89c5132 implement a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. dptr0 and dptr1 are seen by the cpu as dptr and are accessed using the sfr addresses 83h and 84h that are the dph and dpl addresses. the dps bit in auxr1 register (see table 15 ) is used to select whether dptr is t he data pointer 0 or the data pointer 1 (see figure 8-6 ). figure 8-6. dual data pointer implementation 8.3.2 application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block oper ations (copy, compare, search ?) are well served by using one data pointer as a ?source? pointer an d the other one as a ?destination? pointer. below is an example of block move implementati on using the two pointers and coded in assem - bler. the latest c compiler also takes advantage of this feature by providing enhanced algorithm libraries. the inc instruction is a short (2 bytes) and fast (6 cpu clocks) way to manipulate the dps bit in the auxr1 register. however, note that the inc instruction does not directly forces the dps bit to a particular state, but simply toggles it. in si mple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is ?0? or ?1? on entry. ; ascii block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; ends when encountering null character ; note: dps exits opposite of entry state unless an extra inc auxr1 is added auxr1 equ 0a2h move: mov dptr,#source ; address of source inc auxr1 ; switch data pointers mov dptr,#dest ; address of dest mv_loop: inc auxr1 ; switch data pointers movx a,@dptr ; get a byte from source inc dptr ; increment source address inc auxr1 ; switch data pointers movx @dptr,a ; write the byte to dest inc dptr ; increment dest address jnz mv_loop ; check for null terminator end_move: 0 1 dph0 dph1 dpl0 0 1 dps auxr1.0 dph dpl dpl1 dptr dptr0 dptr1
27 4173d?usb?02/06 at89c5132 8.4 registers table 13. psw register psw (s:8eh) ? program status word register reset value = 0000 0000b table 14. auxr register auxr (s:8eh) ? auxiliary control register 76543210 cy ac f0 rs1 rs0 ov f1 p bit number bit mnemonic description 7cy carry flag carry out from bit 1 of alu operands. 6ac auxiliary carry flag carry out from bit 1 of addition operands. 5f0 user definable flag 0. 4 - 3 rs1:0 register bank select bits refer to table 10 for bits description. 2ov overflow flag overflow set by arithmetic operations. 1f1 user definable flag 1 0p parity bit set when acc contains an odd number of 1?s. cleared when acc contains an even number of 1?s. 76543210 - ext16 m0 dphdis xrs1 xrs0 extram ao bit number bit mnemonic description 7- reserved the values read from this bit is indeterminate. do not set this bit. 6 ext16 external 16-bit access enable bit set to enable 16-bit access mode during movx instructions. clear to disable 16-bit access mode and en able standard 8-bit access mode during movx instructions. 5m0 external memory access stretch bit set to stretch rd or wr signals duration to 15 cpu clock periods. clear not to stretch rd or wr signals and set duration to 3 cpu clock periods. 4dphdis dph disable bit set to disable dph output on p2 when executing movx @dptr instruction. clear to enable dph output on p2 when executing movx @dptr instruction. 3 - 2 xrs1:0 expanded ram size bits refer to table 11 for eram size description.
28 4173d?usb?02/06 at89c5132 reset value = x000 1101b 1 extram external ram enable bit set to select the external xram when executing movx @ri or movx @dptr instructions. clear to select the internal exp anded ram when executing movx @ri or movx @dptr instructions. 0ao ale output enable bit set to output the ale signal only during movx instructions. clear to output the ale signal at a constant rate of f cpu /3. bit number bit mnemonic description
29 4173d?usb?02/06 at89c5132 9. special function registers the special function registers ( sfrs ) of the at89c5132 derivatives fall into the categories detailed in table 15 to table 30 . the relative addresses of these sfrs are provided together with their reset values in table 31 . in this table, the bit-address able registers are identified by note 1. table 15. c51 core sfrs mnemonicaddname 76543210 acc e0h accumulator b f0h b register psw d0h program status word cy ac f0 rs1 rs0 ov f1 p sp 81h stack pointer dpl 82h data pointer low byte dph 83h data pointer high byte table 16. system management sfrs mnemonicaddname 76543210 pcon 87h power control smod1 smod0 - - gf1 gf0 pd idl auxr 8eh auxiliary register 0 - ext16 m0 dphdis xrs1 xrs0 extram ao auxr1 a2h auxiliary register 1 - - enboot - gf3 0 - dps nvers fbh version number nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 table 17. pll and system clock sfrs mnemonicaddname 76543210 ckcon 8fh clock control - wdx2 - - - t1x2 t0x2 x2 pllcon e9h pll control r1 r0 - - pllres - pllen plock pllndiv eeh pll n divider - n6 n5 n4 n3 n2 n1 n0 pllrdivefhpll r divider r9r8r7r6r5r4r3r2 table 18. interrupt sfrs mnemonicaddname 76543210 ien0 a8h interrupt enable control 0 ea eaud - es et1 ex1 et0 ex0 ien1 b1h interrupt enable control 1 - eusb - ekb eadc espi ei2c emmc iph0 b7h interrupt priority control high 0 - iphaud - iphs ipht1 iphx1 ipht0 iphx0 ipl0 b8h interrupt priority control low 0 - iplaud - ipls iplt1 iplx1 iplt0 iplx0 iph1 b3h interrupt priority control high 1 - iphusb - iphkb iphadc iphspi iphi2c iphmmc ipl1 b2h interrupt priority control low 1 - iplusb - iplkb ipladc iplspi ipli2c iplmmc
30 4173d?usb?02/06 at89c5132 table 19. port sfrs mnemonicaddname 76543210 p0 80h 8-bit port 0 p1 90h 8-bit port 1 p2 a0h 8-bit port 2 p3 b0h 8-bit port 3 p4 c0h 8-bit port 4 p5 d8h4-bit port 5 ---- table 20. flash memory sfr mnemonicaddname 76543210 fcon d1h flash control fpl3 fpl 2 fpl1 fpl0 fps fmod1 fmod0 fbusy table 21. timer sfrs mnemonicaddname 76543210 tcon 88h timer/counter 0 and 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 tl0 8ah timer/counter 0 low byte th0 8ch timer/counter 0 high byte tl1 8bh timer/counter 1 low byte th1 8dh timer/counter 1 high byte wdtrst a6h watchdog timer reset wdtprga7hwatchdog timer program -----wto2wto1wto0 table 22. audio interface sfrs mnemonicaddname 76543210 audcon0 9ah audio control 0 just4 just3 just2 just1 just0 pol dsiz hlr audcon1 9bh audio control 1 src drqen msreq mudrn - dup1 dup0 auden audsta 9ch audio status sreq udrn aubusy ----- auddat 9dh audio data aud7 aud6 aud5 aud4 aud3 aud2 aud1 aud0 audclk ech audio clock divider - - - aucd4 aucd3 aucd2 aucd1 aucd0
31 4173d?usb?02/06 at89c5132 table 23. usb controller sfrs mnemonicaddname 76543210 usbcon bch usb global control usbe suspcl k sdrmwu p - uprsm rmwupe confg fadden usbaddr c6h usb address fen uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 usbint bdh usb global interrupt - - wupcpu eorint sofint - - spint usbien beh usb global interrupt enable - - ewupcp u eeorint esofint - - espint uepnumc7husb endpoint number ------epnum1epnum0 uepconx d4h usb endpoint x cont rol epen - - - dtgl epdir eptype1 eptype0 uepstax ceh usb endpoint x status dir - stallrq txrdy stlcrc rxsetu p rxout txcmp ueprstd5husb endpoint reset ----ep3rstep2rstep1rstep0rst uepintf8husb endpoint interrupt ----ep3intep2intep1intep0int uepienc2husb endpoint interrupt enable----ep3inteep2inteep1inteep0inte uepdatx cfh usb endpoint x fifo data fdat7 fdat6 fdat5 fdat4 fdat3 fdat2 fdat1 fdat0 ubyctx e2h usb endpoint x byte counter ? byct6 byct5 byct4 byct3 byct2 byct1 byct0 ufnuml bah usb frame number low fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 ufnumh bbh usb frame number high - - crcok crcerr - fnum10 fnum9 fnum8 usbclkeahusb clock divider ------usbcd1usbcd0 table 24. mmc controller sfrs mnemonicaddname 76543210 mmcon0 e4h mmc control 0 drptr dtptr crptr ctptr mblock dfmt rfmt crcdis mmcon1 e5h mmc control 1 blen3 blen2 blen1 blen0 datdir daten respen cmden mmcon2 e6h mmc control 2 mmcen dcr ccr - - datd1 datd0 flowc mmsta deh mmc control and status - - cbusy crc16s datfs crc7s respfs cflck mmint e7h mmc interrupt mcbi eori eoci eofi f2fi f1fi f2ei f1ei mmmsk dfh mmc interrupt mask mcbm eorm eocm eofm f2fm f1fm f2em f1em mmcmd ddh mmc command mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 mmdat dch mmc data md7 md6 md5 md4 md3 md2 md1 md0 mmclk edh mmc clock divider mmcd7 mmcd6 mmcd5 mmcd4 mmcd3 mmcd2 mmcd1 mmcd0 table 25. ide interface sfr mnemonicaddname 76543210 dat16h f9h high order data byte d15 d14 d13 d12 d11 d10 d9 d8
32 4173d?usb?02/06 at89c5132 table 26. serial i/o port sfrs mnemonicaddname 76543210 scon 98h serial control fe/sm0 sm1 sm2 ren tb8 rb8 ti ri sbuf 99h serial data buffer saden b9h slave address mask saddr a9h slave address bdrcon 92h baud rate control - - - brr tbck rbck spd src brl 91h baud rate reload table 27. spi controller sfrs mnemonicaddname 76543210 spcon c3h spi control spr2 spen ssdis mstr cpol cpha spr1 spr0 spsta c4h spi status spif wcol - modf ---- spdat c5h spi data spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 table 28. special register mnemonicaddname 76543210 sscon 93h reserved sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 sssta 94h reserved ssc4 ssc3 ssc2 ssc1 ssc0 0 0 0 ssdat 95h reserved ssd7 ssd6 ssd5 ssd4 ssd3 ssd2 ssd1 ssd0 ssadr 96h reserved ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssgc table 29. keyboard interface sfrs mnemonicaddname 76543210 kbcon a3h keyboard control kinl3 kinl2 kinl1 kinl0 kinm3 kinm2 kinm1 kinm0 kbsta a4h keyboard status kpde - - - kinf3 kinf2 kinf1 kinf0 table 30. a/d controller sfrs mnemonicaddname 76543210 adcon f3h adc control - adidl aden adeoc adsst - - adcs adclk f2h adc clock divider - - - adcd4 adcd3 adcd2 adcd1 adcd0 addlf4hadc data low byte ------adat1adat0 addh f5h adc data high byte adat9 adat8 adat7 adat6 adat5 adat4 adat3 adat2
33 4173d?usb?02/06 at89c5132 reserved notes: 1. sfr registers with least significant nibble address equal to 0 or 8 are bit-addressable. 2. nvers reset value depends on the silicon version: 1000 0011 for at89c5132 product 3. fcon register is only available in at89c5132 product. 4. fcon reset value is 00h in case of reset with hardware condition. 5. ckcon reset value depends on the x2b bit (programmed or unprogrammed) in the hardware byte. table 31. sfr addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h uepint 0000 0000 dat16h xxxx xxxx nvers (2) xxxx xxxx ffh f0h b (1) 0000 0000 adclk 0000 0000 adcon 0000 0000 addl 0000 0000 addh 0000 0000 f7h e8h pllcon 0000 1000 usbclk 0000 0000 audclk 0000 0000 mmclk 0000 0000 pllndiv 0000 0000 pllrdiv 0000 0000 efh e0h acc (1) 0000 0000 ubyctlx 0000 0000 mmcon0 0000 0000 mmcon1 0000 0000 mmcon2 0000 0000 mmint 0000 0011 e7h d8h p5 (1) xxxx 1111 mmdat 1111 1111 mmcmd 1111 1111 mmsta 0000 0000 mmmsk 1111 1111 dfh d0h psw (1) 0000 0000 fcon (3) 1111 0000 (4) uepconx 0000 0000 ueprst 0000 0000 d7h c8h uepstax 0000 0000 uepdatx 0000 0000 cfh c0h p4 (1) 1111 1111 uepien 0000 0000 spcon 0001 0100 spsta 0000 0000 spdat xxxx xxxx usbaddr 1000 0000 uepnum 0000 0000 c7h b8h ipl0 (1) x000 0000 saden 0000 0000 ufnuml 0000 0000 ufnumh 0000 0000 usbcon 0000 0000 usbint 0000 0000 usbien 0001 0000 bfh b0h p3 (1) 1111 1111 ien1 0000 0000 ipl1 0000 0000 iph1 0000 0000 iph0 x000 0000 b7h a8h ien0 (1) 0000 0000 saddr 0000 0000 afh a0h p2 (1) 1111 1111 auxr1 xxxx 00x0 kbcon 0000 1111 kbsta 0000 0000 wdtrst xxx xxxx wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf xxxx xxxx audcon0 0000 1000 audcon1 1011 0010 audsta 1100 0000 auddat 1111 1111 9fh 90h p1 (1) 1111 1111 brl 0000 0000 bdrcon xxx0 0000 sscon 0000 0000 sssta 1111 1000 ssdat 1111 1111 ssadr 1111 1110 97h 88h tcon (1) 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr x000 1101 ckcon 0000 000x (5) 8fh 80h p0 (1) 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00xx 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
34 4173d?usb?02/06 at89c5132 10. interrupt system the at89c5132, like other control-oriented comput er architectures, employ a program interrupt method. this operation branches to a subroutine and performs some service in response to the interrupt. when the subroutine terminates, execut ion resumes at the point where the interrupt occurred. interrupts may occur as a result of inte rnal at89c5132 activity (e.g., timer overflow) or at the initiation of electrical si gnals external to the microcontrolle r (e.g., keyboard). in all cases, interrupt operation is programmed by the system designer, who determines priority of interrupt service relative to normal code execution and other interrupt service routin es. all of the interrupt sources are enabled or disabled by the system designer and may be manipulated dynamically. a typical interrupt event chain occurs as follows: 1. an internal or external device initiates an interrupt-request signal. the at89c5132, latch this event into a flag buffer. 2. the priority of the flag is compared to the priority of other interrupts by the interrupt han - dler. a high priority causes the h andler to set an interrupt flag. 3. this signals the instruction execution unit to execute a context switch. this context switch breaks the current flow of instruction sequences. the execution unit completes the current instruction prior to a save of the program counter (pc) and reloads the pc with the start address of a software service routine. 4. the software service routine executes assi gned tasks and as a final activity performs a reti (return from interr upt) instruction. this instruction signals co mpletion of the inter - rupt, resets the interrupt-in-progress priority and reloads the program counter. program operation then continues from the original point of interruption. table 32. interrupt system signals six interrupt registers are used to control the in terrupt system. two 8-bit registers are used to enable separately the interrupt sour ces: ien0 and ien1 registers (see table 35 and table 36 ). four 8-bit registers are used to establish the prio rity level of the sources: iph0, ipl0, iph1 and ipl1 registers (see table 10-1 to table 39 ). 10.1 interrupt system priorities each of the interrupt sources on the at89c5132 can be individually programmed to one of four priority levels. this is accomplis hed by one bit in the interrupt priority high registers (iph0 and iph1) and one bit in the interrupt priority low registers (ipl0 and ipl1). this provides each interrupt source four possible priority levels according to table 33 . signal name type description alternate function int0 i external interrupt 0 see section "external interrupts", page 37. p3.2 int1 i external interrupt 1 see section ?external interrupts?, page 37. p3.3 kin3:0 i keyboard interrupt inputs see section ?keyboard interface?, page 152. p1.3:0
35 4173d?usb?02/06 at89c5132 table 33. priority levels a low-priority interr upt is always interrupted by a higher prio rity interrupt but not by another inter - rupt of lower or equal priority. higher priority interrupts ar e serviced before lower priority interrupts. the response to simultaneous occurrence of equal pr iority interrupts is determined by an internal hardware polling sequence detailed in table 34 . thus within each priority level there is a second priority structure de termined by the polling sequence. the interrupt control system is shown in figure 10-1 . table 34. priority within same level iphxx iplxx priority level 0 0 0 lowest 011 102 1 1 3 highest interrupt name priority number interrupt address vectors interrupt request flag cleared by hardware (h) or by software (s) int0 0 (highest priority) c:0003h h if edge, s if level timer 0 1 c:000bh h int1 2 c:0013h h if edge, s if level timer 1 3 c:001bh h serial port 4 c:0023h s reserved 5 audio interface 6 c:0033h s mmc interface 7 c:003bh s two-wire controller 8 c:0043h s spi controller 9 c:004bh s a-to-d converter 10 c:0053h s keyboard 11 c:005bh s reserved 12 c:0063h - usb 13 c:006bh s reserved 14 (lowest priority) c:0073h -
36 4173d?usb?02/06 at89c5132 figure 10-1. interrupt control system ei2c ien1.1 emmc ien1.0 eusb ien1.6 espi ien1.2 ex0 ien0.0 00 01 10 11 external interrupt 0 int0 ea ien0.7 ex1 ien0.2 external interrupt 1 int1 et0 ien0.1 timer 0 et1 ien0.3 timer 1 eaud ien0.6 audio interface eadc ien1.3 a to d converter spi controller usb controller ekb ien1.4 keyboard mmc controller two-wire controller iph/l interrupt enable lowest priority interrupts highest kin3:0 priority enable sck si so scl sda 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 priority interrupts es ien0.4 serial port 00 01 10 11 txd rxd mclk mdat mcmd ain1:0 d+ d-
37 4173d?usb?02/06 at89c5132 10.2 external interrupts 10.2.1 int1:0 inputs external interrupts int0 and int1 ( intn , n = 0 or 1) pins may each be programmed to be level- triggered or edge-triggered, dependent upon bits it0 and it1 ( itn , n = 0 or 1) in tcon register as shown in figure 10-2 . if itn = 0, intn is triggered by a low level at the pin. if itn = 1, intn is negative-edge triggered. external interrupts are enabled with bits ex0 and ex1 ( exn , n = 0 or 1) in ien0. events on intn set the interrupt request flag ien in tcon register. if the interrupt is edge-triggered, the request flag is cleared by hardware when vectoring to the interrupt service routine. if the interrupt is level-triggered, the in terrupt service routine must clear the request flag and the interrupt must be deasserted before the end of the interrupt service routine. int0 and int1 inputs provide both the c apability to exit from power- down mode on low level sig - nals as detailed in section ?exiting power-down mode?, page 47 . figure 10-2. int1:0 input circuitry 10.2.2 kin3:0 inputs external interrupts kin0 to kin3 provide the capability to connect a matrix keyboard. for detailed information on these inputs, refer to section ?keyboard interface?, page 152 . 10.2.3 input sampling external interrupt pins ( int1:0 and kin3:0) are sampled once per peripheral cycle (6 peripheral clock periods) (see figure 10-3 ). a level-triggered interrupt pin held low or high for more than 6 peripheral clock periods (12 osc illator in standard mode or 6 oscillator clock periods in x2 mode) guarantees detection. edge-triggered external inte rrupts must hold the request pin low for at least 6 peripheral clock periods. figure 10-3. minimum pulse timings 0 1 int0/1 it0/1 tcon.0/2 ex0/1 ien0.0/2 int0/1 interrupt request ie0/1 tcon.1/3 edge-triggered interrupt level-triggered interrupt 1 cycle 1 cycle > 1 peripheral cycle 1 cycle > 1 peripheral cycle
38 4173d?usb?02/06 at89c5132 10.3 registers table 35. ien0 register ien0 (s:a8h) ? interrupt enable register 0 reset value = 0000 0000b table 36. ien1 register ien1 (s:b1h) ? interrupt enable register 1 76543210 ea eaud ? es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit set to enable all interrupts. clear to disable all interrupts. if ea = 1, each interrupt source is individual ly enabled or disabled by setting or clearing its interrupt enable bit. 6 eaud audio interface interrupt enable bit set to enable audio interface interrupt. clear to disable audio interface interrupt. 5? reserved the values read from this bit is always 0. do not set this bit. 4es serial port interrupt enable bit set to enable serial port interrupt. clear to disable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit set to enable timer 1 overflow interrupt. clear to disable timer 1 overflow interrupt. 2 ex1 external interrupt 1 enable bit set to enable external interrupt 1. clear to disable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit set to enable timer 0 overflow interrupt. clear to disable timer 0 overflow interrupt. 0 ex0 external interrupt 0 enable bit set to enable external interrupt 0. clear to disable external interrupt 0. 76543210 - eusb ? ekb eadc espi ei2c emmc
39 4173d?usb?02/06 at89c5132 reset value = 0000 0000b bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6eusb usb interface interrupt enable bit set this bit to enable usb interrupts. clear this bit to disable usb interrupts. 5- reserved the value read from this bit is always 0. do not set this bit. 4ekb keyboard interface interrupt enable bit set to enable keyboard interrupt. clear to disable keyboard interrupt. 3 eadc a to d converter interrupt enable bit set to enable adc interrupt. clear to disable adc interrupt. 2 espi spi controller interrupt enable bit set to enable spi interrupt. clear to disable spi interrupt. 1ei2c two wire controller interrupt enable bit set to enable two wire interrupt. clear to disable two wire interrupt. 0 emmc mmc interface interrupt enable bit set to enable mmc interrupt. clear to disable mmc interrupt.
40 4173d?usb?02/06 at89c5132 table 10-1. iph0 register iph0 (s:b7h) ? interrupt priority high register 0 reset value = x000 0000b 76543210 - iphaud ? iphs ipht1 iphx1 ipht0 iphx0 bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6 iphaud audio interface interrupt priority level msb refer to table 33 for priority level description. 5iphmp3 mp3 decoder interrupt priority level msb refer to table 33 for priority level description. 4iphs serial port interrupt priority level msb refer to table 33 for priority level description. 3ipht1 timer 1 interrupt priority level msb refer to table 33 for priority level description. 2iphx1 external interrupt 1 priority level msb refer to table 33 for priority level description. 1- reserved the value read from this bit is i ndeterminate. do not set this bit. 0iphx0 external interrupt 0 priority level msb refer to table 33 for priority level description.
41 4173d?usb?02/06 at89c5132 table 37. iph1 register iph1 (s:b3h) ? interrupt priority high register 1 reset value = 0000 0000b 76543210 - iphusb ? iphkb iphadc iphspi iphi2c iphmmc bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6 iphusb usb interrupt priority level msb refer to table 33 for priority level description. 5- reserved the value read from this bit is always 0. do not set this bit. 4 iphkb keyboard interrupt priority level msb refer to table 33 for priority level description. 3 iphadc a to d converter interrupt priority level msb refer to table 33 for priority level description. 2iphspi spi interrupt priority level msb refer to table 33 for priority level description. 1iphi2c two wire controller interrupt priority level msb refer to table 33 for priority level description. 0 iphmmc mmc interrupt priority level msb refer to table 33 for priority level description.
42 4173d?usb?02/06 at89c5132 table 38. ipl0 register ipl0 (s:b8h) ? interrupt priority low register 0 reset value = x000 0000b 76543210 - iplaud ? ipls iplt1 iplx1 iplt0 iplx0 bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6 iplaud audio interface interrupt priority level lsb refer to table 33 for priority level description. 5iplmp3 mp3 decoder interrupt priority level lsb refer to table 33 for priority level description. 4ipls serial port interrupt priority level lsb refer to table 33 for priority level description. 3iplt1 timer 1 interrupt priority level lsb refer to table 33 for priority level description. 2iplx1 external interrupt 1 priority level lsb refer to table 33 for priority level description. 1iplt0 timer 0 interrupt priority level lsb refer to table 33 for priority level description. 0iplx0 external interrupt 0 priority level lsb refer to table 33 for priority level description.
43 4173d?usb?02/06 at89c5132 table 39. ipl1 register ipl1 (s:b2h) ? interrupt priority low register 1 reset value = 0000 0000b 76543210 - iplusb - iplkb ipladc iplspi ipli2c iplmmc bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6iplusb usb interrupt priority level lsb refer to table 33 for priority level description. 5- reserved the value read from this bit is always 0. do not set this bit. 4 iplkb keyboard interrupt priority level lsb refer to table 33 for priority level description. 3 ipladc a to d converter interrupt priority level lsb refer to table 33 for priority level description. 2 iplspi spi interrupt priority level lsb refer to table 33 for priority level description. 1ipli2c two wire controller interrupt priority level lsb refer to table 33 for priority level description. 0 iplmmc mmc interrupt priority level lsb refer to table 33 for priority level description.
44 4173d?usb?02/06 at89c5132 11. power management 2 power reduction modes are implemented in the at89c5132: the idle mode and the power- down mode. these modes are detailed in the fo llowing sections. in addition to these power reduction modes, the clocks of the core and peri pherals can be dynamically divided by 2 using the x2 mode detailed in section ?x2 feature?, page 12 . 11.1 reset in order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high level has to be applied on the rst pin. a bad leve l leads to a wrong initia lization of the internal registers like sfrs, program counter? and to unpr edictable behavior of the microcontroller. a proper device reset initializes the at89c5132 and vectors the cpu to address 0000h. rst input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to v dd as shown in figure 11-1 . a warm reset can be applied either directly on the rst pin or indi - rectly by an internal reset source such as the watchdog timer. resistor value and input characteristics are discussed in the section ?dc characteristics? of the at89c5132 datasheet. the status of the port pins during reset is detailed in table 16 . figure 11-1. reset circuitry and power-on reset table 16. pin conditions in special operating modes note: 1. refer to section ?audio output interface?, page 75 . 11.1.1 cold reset 2 conditions are required before enabling a cpu start-up: ?v dd must reach the specified v dd range ? the level on x1 input pin must be outside the specification (v ih , v il ) if one of these 2 conditions are not met, the mi crocontroller does not start correctly and can exe - cute an instruction fetch from anywhere in the program space. an active level applied on the rst pin must be maintained till bo th of the above conditions are met. a reset is active when the level v ih1 is reached and when the pulse width covers the period of time where v dd and the oscillator are not stabilized. 2 parameters have to be taken into account to determine the reset pulse width: ?v dd rise time, ? oscillator startup time. mode port 0 port 1 port 2 port 3 port 4 port 5 mmc audio reset floating high high high high high floating 1 idle data data data data data data data data power-down data data data data data data data data r rst rst vss to cpu core and peripherals rst vdd + power-on reset rst input circuitry p vdd from internal reset source
45 4173d?usb?02/06 at89c5132 to determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. table 17 gives some capacitor values examples for a minimum r rst of 50 k and different oscillator startup and v dd rise times. table 17. minimum reset capacitor value for a 50 k pull-down resistor (1) note: 1. these values assume v dd starts from 0v to the nominal value. if the time between 2 on/off sequences is too fast, the power-supply de-coup ling capacitors may not be fully discharged, leading to a bad reset sequence. 11.1.2 warm reset to achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) while the oscillator is running. the number of clock periods is mode independent (x2 or x1). 11.1.3 watchdog reset as detailed in section ?watchdog timer?, page 61 , the wdt generates a 96-clock period pulse on the rst pin. in order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 k resistor must be added as shown in figure 11-2 . figure 11-2. reset circuitry for wdt reset-out usage 11.2 reset recommendation to prevent flash corruption an example of bad initializati on situation may occur in an inst ance where the bit enboot in auxr1 register is initialized from the hardware bit bljb upon reset. since this bit allows map - ping of the bootloader in the code area, a reset failure can be critical. if one wants the enboot cleared in order to unm ap the boot from the code area (yet due to a bad reset) the bit enboot in sfrs may be set. if the value of program counter is accidently in the range of the boot memory addresses then a flash access (write or erase) may corrupt the flash on-chip memory. it is recommended to use an external reset circuitry featuring power supply monitoring to prevent system malfunction during periods of insuffici ent power supply voltage (power supply failure, power supply switched off). oscillator start-up time vdd rise time 1 ms 10 ms 100 ms 5 ms 820 nf 1.2 f 12 f 20 ms 2.7 f 3.9 f 12 f r rst rst vss to cpu core and peripherals vdd + p vdd from wdt reset source vss vdd rst 1k to other on-board circuitry
46 4173d?usb?02/06 at89c5132 11.3 idle mode idle mode is a power reduction mode that reduces the power consumption. in this mode, pro - gram execution halts. idle mode freezes the clock to the cpu at known states while the peripherals continue to be clocked (refer to section ?oscillator?, page 12 ). the cpu status before entering idle mode is preserved, i.e., the program counter and program status word reg - ister retain their data for the duration of idle mode. the contents of the sfrs and ram are also retained. the status of the port pins during idle mode is detailed in table 16 . 11.3.1 entering idle mode to enter idle mode, the user must set the idl bit in pcon register (see table 18 ). the at89c5132 enters idle mode upon execution of the instruction that sets idl bit. the instruction that sets idl bit is the last instruction executed. note: if idl bit and pd bit are set simultaneously, the at89c5132 enter power-down mode. then it does not go in idle mode when exiting power-down mode. 11.3.2 exiting idle mode there are 2 ways to exit idle mode: 1. generate an enabled interrupt. ? hardware clears idl bit in pcon register which restores the clock to the cpu. execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated idle mode. the general-purpose flags (gf1 and gf0 in pcon register) may be used to indicate whether an interrupt occurred during normal operation or during idle mode. when idle mode is exited by an interrupt, the interrupt service routine may examine gf1 and gf0. 2. generate a reset. ? a logic high on the rst pin clears id l bit in pcon register directly and asynchronously. this restores the clock to the cpu. program execution momentarily resumes with the instruction im mediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the at89c5132 and vectors the cpu to address c:0000h. note: during the time that executio n resumes, the internal ram cann ot be accessed; however, it is pos - sible for the port pins to be accessed. to avoid u nexpected outputs at the port pins, the instruction immediately following the instruction that activated idle mode should not write to a port pin or to the external ram. 11.4 power-down mode the power-down mode places the at89c5132 in a very low power state. power-down mode stops the oscillator and freezes all cl ocks at known states (refer to the section "oscillator", page 12 ). the cpu status prior to entering power-down mode is preserved, i.e., the program counter, program status word register retain thei r data for the duration of power-down mode. in addition, the sfrs and ram contents are preserved. the status of the port pins during power- down mode is detailed in table 16 . note: v dd may be reduced to as low as v ret during power-down mode to further reduce power dissipa - tion. notice, however, that v dd is not reduced until power-down mode is invoked.
47 4173d?usb?02/06 at89c5132 11.4.1 entering power-down mode to enter power-down mode, set pd bit in pc on register. the at89c5132 enters the power- down mode upon execution of the in struction that sets pd bit. the instruction that sets pd bit is the last instruction executed. 11.4.2 exiting power-down mode if v dd was reduced during the power-down mode, do not exit power-down mode until v dd is restored to the normal operating level. there are 2 ways to exit the power-down mode: 1. generate an enabled external interrupt. ? the at89c5132 provides capabilit y to exit from power-down using int0 , int1 , and kin3:0 inputs. in addition, using kin input provides high or low level exit capability (see section ?keyboard interface?, page 181 ). hardware clears pd bit in pcon register which starts the oscillator and restores the clocks to the cpu and peripherals. using intn input, execution resumes when the input is released (see figure 11-3 ) while using kinx input, execution resumes after counting 1024 clock ensuring the osc illator is restarte d properly (see figure 11-4 ). this behavior is necessary for decoding th e key while it is still pressed. in both cases, execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated power-down mode. note: 1. the external interrupt used to exit powe r-down mode must be config ured as level sensitive ( int0 and int1 ) and must be assigned the highest prio rity. in addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. the execution will only resume when the inte rrupt is deasserted. 2. exit from power-down by exter nal interrupt does not affect the sfrs nor the internal ram content. figure 11-3. power-down exit wa veform using int1:0 figure 11-4. power-down exit wa veform using kin3:0 note: 1. kin3:0 can be high or low-level triggered. 2. generate a reset. int1:0 osc power-down phase oscillator restart active phase active phase kin3:0 1 osc power-down 1024 clock count active phase active phase
48 4173d?usb?02/06 at89c5132 ? a logic high on the rst pin clears pd bit in pcon register directly and asynchronously. this starts the oscillato r and restores the cl ock to the cpu and peripherals. program execution momentarily resumes with the instruction immediately following the instruction that activated power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the at89c51 32 and vectors the cpu to address 0000h. notes: 1. during the time that execution resumes, the internal ram cannot be a ccessed; however, it is possible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately followi ng the instruction that activate d the power-down mode should not write to a port pin or to the external ram. 2. exit from power-down by reset redefines all the sfrs , but does not affect the internal ram content. 11.5 registers table 18. pcon register pcon (s:87h) ? power configuration register reset value = 00xx 0000b 76543210 smod1 smod0 - - gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 set to select double baud rate in mode 1,2 or 3. 6smod0 serial port mode bit 0 set to select fe bit in scon register. clear to select sm0 bit in scon register. 5 - 4 - reserved the value read from these bits is i ndeterminate. do not set these bits. 3gf1 general-purpose flag 1 one use is to indicate whether an interrupt occurred during normal operation or during idle mode. 2gf0 general-purpose flag 0 one use is to indicate whether an interrupt occurred during normal operation or during idle mode. 1pd power-down mode bit cleared by hardware when an interrupt or reset occurs. set to activate the power-down mode. if idl and pd are both set, pd takes precedence. 0idl idle mode bit cleared by hardware when an interrupt or reset occurs. set to activate the idle mode. if idl and pd are both set, pd takes precedence.
49 4173d?usb?02/06 at89c5132 12. timers/counters the at89c5132 implement two general-purpose, 16-b it timers/counters. t hey are identified as timer 0 and timer 1, and can be independently configured to operate in a variety of modes as a timer or as an event counter. when operating as a timer, the timer/counter runs for a pro - grammed length of time, then issues an inte rrupt request. when operating as a counter, the timer/counter counts negative transitions on an external pin. after a preset number of counts, the counter issues an interrupt request. the various operating modes of each timer/counter are described in the following sections. 12.1 timer/counter operations for instance, a basic operation is timer registers thx and tlx (x = 0, 1) connected in cascade to form a 16-bit timer. setting the run control bit (trx) in tcon register (see table 40 ) turns the timer on by allowing the selected input to incr ement tlx. when tlx overflows it increments thx; when thx overflows it sets the timer overflow flag (tfx) in tcon register. setting the trx does not clear the thx and tlx timer registers. timer registers can be accessed to obtain the current count or to enter preset values. they can be read at any time but trx bit must be cleared to preset their values, otherwise the beh avior of the timer/counter is unpredictable. the c/tx# control bit selects timer operation or counter operation by selecting the divided- down peripheral clock or external pin tx as the source for the counted signal. trx bit must be cleared when changing the mode of operation, otherwise the behav ior of the timer/counter is unpredictable. for timer operation (c/tx# = 0), the timer register counts the divided-down peripheral clock. the timer register is incremented once every pe ripheral cycle (6 peripheral clock periods). the timer clock rate is f per /6, i.e., f osc /12 in standard mode or f osc /6 in x2 mode. for counter operation (c/tx# = 1), the timer r egister counts the negative transitions on the tx external input pin. the external input is samp led every peripheral cycles. when the sample is high in one cycle and low in the next one, the counter is incremented. since it takes 2 cycles (12 peripheral clock periods) to recognize a nega tive transition, the maximum count rate is f per /12, i.e., f osc /24 in standard mode or f osc /12 in x2 mode. there are no restrictions on the duty cycle of the external input signal, but to ensure t hat a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. 12.2 timer clock controller as shown in figure 12-1 , the timer 0 (ft0) and timer 1 (ft1) clocks are derived from either the peripheral clock (f per ) or the oscillator clock (f osc ) depending on the t0x2 and t1x2 bits in ckcon register. these cl ocks are issued from the clock controller block as detailed in section ?ckcon register?, page 14 . when t0x2 or t1x2 bit is set, the timer 0 or timer 1 clock fre - quency is fixed and equal to the oscillator clock frequency divided by 2. when cleared, the timer clock frequency is equal to the oscillator clock freq uency divided by 2 in st andard mode or to the oscillator clock frequency in x2 mode.
50 4173d?usb?02/06 at89c5132 figure 12-1. timer 0 and timer 1 clock controller and symbols 12.3 timer 0 timer 0 functions as either a timer or ev ent counter in four modes of operation. figure 12-2 through figure 12-8 show the logical configuration of each mode. timer 0 is controlled by the four lo wer bits of tmod register (see table 41 ) and bits 0, 1, 4 and 5 of tcon register (see table 40 ). tmod register selects the method of timer gating (gate0), timer or counter operation (c/t0#) and mode of operation (m10 and m00). tcon register pro - vides timer 0 control functions: overflow flag (tf0 ), run control bit (tr0), interrupt flag (ie0) and interrupt type control bit (it0). for normal timer operation (gate0 = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int0 to control timer operation. timer 0 overflow (count rolls ov er from all 1s to all 0s) sets tf0 flag generating an interrupt request. it is important to stop time r/counter before changing mode. 12.3.1 mode 0 (13-bit timer) mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (th0 register) with a modulo 32 prescaler implemented with the lower five bits of tl0 register (see figure 12-2 ). the upper three bits of tl0 register are indeter minate and should be ignored. prescaler over - flow increments th0 register. figure 12-3 gives the overflow period calculation formula. figure 12-2. timer/counter x (x = 0 or 1) in mode 0 figure 12-3. mode 0 overflow period formula per clock tim0 clock osc clock 0 1 t0x2 ckcon.1 2 timer 0 clock timer 0 clock symbol per clock tim1 clock osc clock 0 1 t1x2 ckcon.2 2 timer 1 clock timer 1 clock symbol timx clock trx tcon reg tfx tcon reg 0 1 gatex tmod reg 6 overflow timer x interrupt request c/tx# tmod reg thx (8 bits) tlx (5 bits) intx tx 6 ? (16384 ? (thx, tlx)) tfx per = f timx
51 4173d?usb?02/06 at89c5132 12.3.2 mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit timer wit h th0 and tl0 registers connected in cascade (see figure 12-4 ). the selected input increments tl0 register. figure 12-5 gives the overflow period calculation formula when in timer mode. figure 12-4. timer/counter x (x = 0 or 1) in mode 1 figure 12-5. mode 1 overflow period formula 12.3.3 mode 2 (8-bit timer with auto-reload) mode 2 configures timer 0 as an 8-bit timer (tl0 register) that automatically reloads from th0 register (see table 42 ). tl0 overflow sets tf0 flag in tcon register and reloads tl0 with the contents of th0, which is pres et by software. when the interr upt request is serviced, hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to th0 register. figure 12-7 gives the autoreload period calculation formula when in timer mode. figure 12-6. timer/counter x (x = 0 or 1) in mode 2 figure 12-7. mode 2 autoreload period formula 12.3.4 mode 3 (two 8-bit timers) mode 3 configures timer 0 such that register s tl0 and th0 operate as separate 8-bit timers (see figure 12-8 ). this mode is provided for applicati ons requiring an additional 8-bit timer or trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx tx timx clock 6 6 ? (65536 ? (thx, tlx)) tfx per = f timx trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx tx timx clock 6 tfx per = f timx 6 ? (256 ? thx)
52 4173d?usb?02/06 at89c5132 counter. tl0 uses the timer 0 control bits c/t0# and gate0 in tmod register, and tr0 and tf0 in tcon register in the normal manner. th0 is locked into a timer function (counting f tf1 /6) and takes over use of the timer 1 interrupt (tf1) and run control (tr1) bits. thus, oper - ation of timer 1 is restricted when timer 0 is in mode 3. figure 12-7 gives the autoreload period calculation formulas for both tf0 and tf1 flags. figure 12-8. timer/counter 0 in mode 3: two 8-bit counters figure 12-9. mode 3 overflow period formula 12.4 timer 1 timer 1 is identical to timer 0 excepted for mo de 3 which is a hold-c ount mode. following com - ments help to understand the differences: ? timer 1 functions as either a timer or event counter in three modes of operation. figure 12- 2 through figure 12-6 show the logical configuration for modes 0, 1, and 2. timer 1?s mode 3 is a hold-count mode. ? timer 1 is controlled by the four hi gh-order bits of tmod register (see table 41 ) and bits 2, 3, 6 and 7 of tcon register (see figure 40 ). tmod register selects the method of timer gating (gate1), timer or counter operation (c/t1#) and mode of operation (m11 and m01). tcon register provides timer 1 control function s: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and inte rrupt type control bit (it1). ? timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. ? for normal timer operation (gate1 = 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr1 allows external pin int1 to control timer operation. ? timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag generating an interrupt request. ? when timer 0 is in mode 3, it uses timer 1?s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applicat ions that do not require an interrupt (such as a baud rate generator for the serial port) and sw itch timer 1 in and out of mode 3 to turn it off and on. ? it is important to stop the timer/counter before changing modes. tr0 tcon.4 tf0 tcon.5 int0 0 1 gate0 tmod.3 overflow timer 0 interrupt request c/t0# tmod.2 tl0 (8 bits) tr1 tcon.6 th0 (8 bits) tf1 tcon.7 overflow timer 1 interrupt request t0 tim0 clock 6 tim0 clock 6 tf0 per = f tim0 6 ? (256 ? tl0) tf1 per = f tim0 6 ? (256 ? th0)
53 4173d?usb?02/06 at89c5132 12.4.1 mode 0 (13-bit timer) mode 0 configures timer 1 as a 13-bit timer, wh ich is set up as an 8-bit timer (th1 register) with a modulo-32 prescaler implemented with t he lower 5 bits of the tl1 register (see figure 12- 2 ). the upper 3 bits of tl1 register are ignore d. prescaler overflow increments th1 register. 12.4.2 mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit timer wit h th1 and tl1 registers connected in cascade (see figure 12-4 ). the selected input increments tl1 register. 12.4.3 mode 2 (8-bit timer with auto-reload) mode 2 configures timer 1 as an 8-bit timer (tl1 register) with automatic reload from th1 reg - ister on overflow (see figure 12-6 ). tl1 overflow sets tf1 flag in tcon register and reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. 12.4.4 mode 3 (halt) placing timer 1 in mode 3 causes it to halt and ho ld its count. this can be used to halt timer 1 when tr1 run control bit is not availa ble i.e. when timer 0 is in mode 3. 12.5 interrupt each timer handles one interrupt source that is t he timer overflow flag tf0 or tf1. this flag is set every time an overflow occurs. flags are cl eared when vectoring to the timer interrupt rou - tine. interrupts are enabled by setting etx bit in ien0 register. this assumes interrupts are globally enabled by setting ea bit in ien0 register. figure 12-10. timer interrupt system tf0 tcon.5 et0 ien0.1 timer 0 interrupt request tf1 tcon.7 et1 ien0.3 timer 1 interrupt request
54 4173d?usb?02/06 at89c5132 12.6 registers table 40. tcon register tcon (s:88h) ? timer/counter control register reset value = 0000 0000b table 41. tmod register tmod (89:h) - timer/counter 0 and 1 modes 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7tf1 timer 1 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer/counter 1. set to turn on timer/counter 1. 5tf0 timer 0 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer/counter 0. set to turn on timer/counter 0. 3ie1 interrupt 1 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it1). set by hardware when external interrupt is detected on int1 pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int1 ). set to select falling edge active ( edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it0). set by hardware when external interrupt is detected on int0 pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int0 ). set to select falling edge active ( edge triggered) for external interrupt 0. 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00
55 4173d?usb?02/06 at89c5132 reset value = 0000 0000b notes: 1. reloaded from th1 at overflow. 2. reloaded from th0 at overflow. table 42. th0 register th0 (s:8ch) ? timer 0 high byte register reset value = 0000 0000b bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int1 pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer select bit clear for timer operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 count s negative transitions on external pin t1. 5m11 timer 1 mode select bits m11 m01 operating mode 0 0 mode 0: 8-bit timer/counter (th1) with 5-bit prescaler (tl1). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl1). (1) 1 1 mode 3: timer 1 halted. retains count. 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer/counter 0 only while int0 pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer select bit clear for timer operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 count s negative transitions on external pin t0. 1 m10 timer 0 mode select bit m10 m00 operating mode 0 0 mode 0: 8-bit timer/counter (th0) with 5-bit prescaler (tl0). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl0). (2) 1 1 mode 3: tl0 is an 8-bit timer/counter. th0 is an 8-bit timer using timer 1?s tr0 and tf0 bits. 0 m00 76543210 -------- bit number bit mnemonic description 7:0 high byte of timer 0
56 4173d?usb?02/06 at89c5132 table 43. tl0 register tl0 (s:8ah) ? timer 0 low byte register reset value = 0000 0000b table 44. th1 register th1 (s:8dh) ? timer 1 high byte register reset value = 0000 0000b table 45. tl1 register tl1 (s:8bh) ? timer 1 low byte register reset value = 0000 0000b 76543210 -------- bit number bit mnemonic description 7:0 low byte of timer 0 76543210 -------- bit number bit mnemonic description 7:0 high byte of timer 1 76543210 -------- bit number bit mnemonic description 7:0 low byte of timer 1
57 4173d?usb?02/06 at89c5132 13. watchdog timer the at89c5132 implement a hardware watchdog timer (wdt) that automatically resets the chip if it is allowed to time out. the wdt provides a means of recovering from routines that do not complete successfully due to so ftware or hardware malfunctions. 13.1 description the wdt consists of a 14-bit prescaler followed by a 7-bit programmable counter. as shown in figure 13-1 , the 14-bit prescaler is fed by the wdt clock detailed in section "watchdog clock controller", page 57 . the watchdog timer reset register (wdtrst, see table 47 ) provides control access to the wdt, while the watchdog timer program register (wdtprg, see figure 48 ) provides time-out period programming. three operations control the wdt: ? chip reset clears and disables the wdt. ? programming the time-out value to the wdtprg register. ? writing a specific two-byte sequence to the wdtrst register clears and enables the wdt. figure 13-1. wdt block diagram 13.2 watchdog clock controller as shown in figure 13-2 the wdt clock (f wdt ) is derived from either the peripheral clock (f per ) or the oscillator clock (f osc ) depending on the wt x2 bit in ckcon register. these clocks are issued from the clock controller block as detailed in section "clock controller", page 12 . when wtx2 bit is set, the wdt clock frequency is fi xed and equal to the os cillator clock frequency divided by 2. when cleared, the wdt clock frequency is equal to t he oscillator clock frequency divided by 2 in sta ndard mode or to the oscillato r clock frequency in x2 mode. figure 13-2. wdt clock controller and symbol wto2:0 wdtprg.2:0 wdt clock 6 system 1eh-e1h decoder wdtrst 14-bit prescaler rst 7-bit counter rst to internal en rst match set ov osc clock rst pulse generator reset reset per clock wdt clock osc clock 0 1 wtx2 ckcon.6 2 wdt clock wdt clock symbol
58 4173d?usb?02/06 at89c5132 13.3 watchdog operation after reset, the wdt is disabled. the wdt is ena bled by writing the sequence 1eh and e1h into the wdtrst register. as soon as it is enabled, there is no way except the chip reset to disable it. if it is not cleared using the previous seq uence, the wdt overflows and forces a chip reset. this overflow genera tes a high level 96 oscillator periods pulse on the rst pin to globally reset the application. (refer to section ?power management?, page 48 ) the wdt time-out period can be adjusted using wt o2:0 bits located in the wdtprg register accordingly to the formula shown in figure 13-3 . in this formula, wtoval represents the decimal value of wto2:0 bits. table 48 reports the time-out period depending on the wdt frequency. figure 13-3. wdt time-out formula notes: 1. these frequencies are achieved in x1 mode or in x2 mode when wtx2 = 1: f wdt = f osc 2. 2. these frequencies are achieved in x2 mode when wtx2 = 0: f wdt = f osc . 13.3.1 wdt behavior during idle and power-down modes operation of the wdt during power redu ction modes deserves special attention. the wdt continues to count while the at89c5132 are in idle mode. this means that the user must dedicate some internal or external hardware to service the wdt during idle mode. one approach is to use a peripheral timer to gener ate an interrupt request when the timer over - flows. the interrupt service routine then clears the wdt, reloads the peripheral timer for the next service period and puts the at89c5132 back into idle mode. the power-down mode stops all phase clocks. th is causes the wdt to stop counting and to hold its count. the wdt resumes counting from wher e it left off if the power-down mode is ter - minated by int0 , int1 or keyboard interrupt. to ensure that the wdt does not overflow shortly after exiting the power-down mode, it is re commended to clear the wdt just before entering power-down mode. the wdt is cleared and disabled if the power-down mode is terminated by a reset. table 46. wdt time-out computation wto2 wto1 wto0 f wdt (ms) 6 mhz (1) 8 mhz (1) 10 mhz (1) 12 mhz (2) 16 mhz (2) 20 mhz (2) 0 0 0 16.38 12.28 9.83 8.19 6.14 4.92 0 0 1 32.77 24.57 19.66 16.38 12.28 9.83 0 1 0 65.54 49.14 39.32 32.77 24.57 19.66 0 1 1 131.07 98.28 78.64 65.54 49.14 39.32 1 0 0 262.14 196.56 157.29 131.07 98.28 78.64 1 0 1 524.29 393.1 314.57 262.14 196.56 157.29 1 1 0 1049 786.24 629.15 524.29 393.12 314.57 1 1 1 2097 1572 1258 1049 786.24 629.15 wdt to = f wdt 6 ? ( 2 14 ? 2 wtoval )
59 4173d?usb?02/06 at89c5132 13.4 registers table 47. wdtrst register wdtrst (s:a6h write only) ? watchdog timer reset register reset value = xxxx xxxxb table 48. wdtprg register wdtprg (s:a7h) ? watchdog timer program register reset value = xxxx x000b 76543210 -------- bit number bit mnemonic description 7-0 - watchdog control value . 76543210 - - - - - wto2 wto1 wto0 bit number bit mnemonic description 7-3 - reserved the values read from these bits are i ndeterminate. do not set these bits. 2-0 wto2:0 watchdog timer time-out selection bits refer to table 46 for time-out periods.
60 4173d?usb?02/06 at89c5132 14. audio output interface the at89c5132 implement an audio output interfac e allowing the audio bitstream to be output in various formats. it is compatible wit h right and left justification pcm and i 2 s formats and thanks to the on-chip pll (see section ?clock controller?, page 12 ) allows connection of almost all of the commercial audio dac families available on the market. 14.1 description the c51 core interfaces to the audio interface th rough five special function registers: audcon0 and audcon1, the audio control registers (see table 51 and table 52 ); audsta, the audio status register (see table 53 ); auddat, the audio data register (see table 54 ); and audclk, the audio clock divider register (see table 55 ). figure 14-1 shows the audio interface block diagram, blocks are detailed in the following sections. figure 14-1. audio interface block diagram 14.2 clock generator the audio interface clock is generated by division of the pll clock. the division factor is given by aucd4:0 bits in audclk register. figure 14-2 shows the audio interface clock generator and its calculation formula. the audio inte rface clock frequency depends on the audio dac used. aud clock udrn audsta.6 0 1 dsiz audcon0.1 dsel clock generator dclk dout sclk just4:0 audcon0.7:3 pol audcon0.2 auden audcon1.0 hlr audcon0.0 8 data converter audio data from c51 dup1:0 audcon1.2:1 sreq audsta.7 audio buffer aubusy audsta.5 data ready auddat 16
61 4173d?usb?02/06 at89c5132 figure 14-2. audio clock generator and symbol as soon as audio interface is enabled by setting auden bit in audcon1 register, the master clock generated by the pll is output on the sclk pin which is the dac system clock. this clock is output at 256 or 384 times the sampling fr equency depending on the dac capabilities. hlr bit in audcon0 register must be set according to this rate for properly generating the audio bit clock on the dclk pin and the word selection cl ock on the dsel pin. these clocks are not gen - erated when no data is available at the data converter input. for dac compatibility, the bit clock frequency is programmable for outputting 16 bits or 32 bits per channel using the dsiz bit in audcon0 register (see section "data converter", page 61 ), and the word selection signal is programmable for outputting left channel on low or high level according to pol bit in audco n0 register as shown in figure 14-3 . figure 14-3. dsel output polarity 14.3 data converter the data converter block converts the audio str eam input from the 16-bit parallel format to a serial format. for accepting all pcm formats and i 2 s format, just4:0 bits in audcon0 register are used to shift the data output point. as shown in figure 14-4 , these bits allow msb justifica - tion by setting just4:0 = 00000, lsb just ification by setting just4:0 = 10000, i 2 s justification by setting just4:0 = 00001, and more than 16-bit lsb justification by filling the low significant bits with logic 0. table 49. dac format programing examples aucd4:0 audclk audio interface clock audclk pllclk au c d1 + --------------------------- = audio clock symbol aud clock pll clock left channel right channel pol = 1 pol = 0 left channel right channel dac format pol dsiz just4:0 16-bit i 2 s 0 0 00001 > 16-bit i 2 s 0 1 00001 16-bit pcm 1 0 00000 18-bit pcm lsb justified 1 1 01110 20-bit pcm lsb justified 1 1 01100 20-bit pcm msb justified 1 1 00000
62 4173d?usb?02/06 at89c5132 figure 14-4. audio output format as soon as first audio data is input to the data converter, it enables the clock generator for gen - erating the bit and word clocks. 14.4 audio buffer in voice or sound playing mode, the audio stream comes from the c51 core through an audio buffer. the data is in 8-bit format and is sampl ed at 8 khz. the audio buffer adapts the sample format and rate. the sample format is extended to 16 bits by filling the lsb to 00h. rate is adapted to the dac rate by duplicating the dat a using dup1:0 bits in audcon1 register according to table 50 . the audio buffer interfaces to the c51 core through three flags: the sample request flag (sreq in audsta register), the under-run flag ( undr in audsta register) and the busy flag (aubusy in audsta register). sreq an d undr can generate an interrupt request as explained in section "interrupt request", page 63 . the buffer size is 8 bytes large. sreq is set when the samples number switches from 4 to 3 and reset when the samples number switches from 4 to 5; undr is set when the buffer becom es empty signaling that the audio interface ran out of samples; and aubusy is set when the buffer is full. dsel dclk dout msb i2s format with dsiz = 0 and just4:0 = 00001. lsb b14 msb lsb b14 b1 b1 dsel dclk dout msb i2s format with dsiz = 1 and just4:0 = 00001. lsb b14 msb lsb b14 1 2 3 13141516 1 2 3 13 14 15 16 left channel right channel 123 1718 32 1 2 3 17 18 32 dsel dclk dout b14 msb/lsb justified format with dsiz = 0 and just4:0 = 00000. msb b1 b15 msb b1 lsb lsb 1 2 3 13141516 1 2 3 13 14 15 16 left channel right channel left channel right channel dsel dclk dout 16-bit lsb justified format with dsiz = 1 and just4:0 = 10000. 11618 32 32 left channel right channel 17 31 msb b14 lsb b1 msb b14 lsb b1 11618 17 31 dsel dclk dout 18-bit lsb justified format with dsiz = 1 and just4:0 = 01110. 115 3032 left channel right channel 16 31 msb b16 b2 1 b1 lsb msb b16 b2 b1 lsb 15 30 32 16 31
63 4173d?usb?02/06 at89c5132 table 50. sample duplication factor 14.5 interrupt request the audio interrupt request can be generated by two sources when in c51 audio mode: a sam - ple request when sreq flag in audsta register is set to logic 1, and an under-run condition when udrn flag in audsta register is set to logic 1. both sources can be enabled separately by masking one of them using the msreq a nd mudrn bits in audc on1 register. a global enable of the audio interface is provided by setting the eaud bit in ien0 register. the interrupt is requested each time one of the tw o sources is set to one. the source flags are cleared by writing some data in the audio buffer through auddat, but the global audio interrupt flag is cleared by hardware when the interrupt service routine is executed. figure 14-5. audio interface interrupt system 14.6 voice or sound playing in voice or sound playing mode, the operations required are to configure the pll and the audio interface according to the dac selected. the audi o clock is programmed to generate the 256fs or 384fs. the data flow sent by the c51 is then regulated by interrupt and data is loaded 4 bytes by 4 bytes. figure 14-6 shows the configuration flow of the audio interface when in voice or sound mode. dup1 dup0 factor 0 0 no sample duplication, dac rate = 8 khz (c51 rate). 0 1 one sample duplication, dac rate = 16 khz (2 x c51 rate). 1 0 two samples duplication, dac rate = 32 khz (4 x c51 rate). 1 1 three samples duplication, dac rate = 48 khz (6 x c51 rate). sreq audsta.7 audio interrupt request udrn audsta.6 msreq audcon1.5 eaud ien0.6 mudrn audcon1.4
64 4173d?usb?02/06 at89c5132 figure 14-6. voice or sound mode audio flows note: 1. an under-run occurrence signifies that the c51 core did not respond to the previous sample request interrupt. it may nev er occur for a correct voice/sound generation. it is the user?s responsibility to mask it or not. 14.7 registers table 51. audcon0 register audcon0 (s:9ah) ? audio interface control register 0 reset value = 0000 1000b table 52. audcon1 register audcon1 (s:9bh) ? audio interface control register 1 load 8 samples in the audio buffer voice/song mode configuration configure interface hlr = x dsiz = x pol = x just4:0 = xxxxxb dup1:0 = xx program audio clock enable dac system clock auden = 1 wait for dac enable time enable interrupt set msreq & mudrn 1 eaud = 1 audio interrupt service routine under-run condition 1 load 4 samples in the audio buffer sample request? sreq = 1? 76543210 just4 just3 just2 just1 just0 pol dsiz hlr bit number bit mnemonic description 7-3 just4:0 audio stream justification bits refer to section "data converter", page 61 for bits description. 2pol dsel signal output polarity set to output the left channel on high level of dsel output (pcm mode). clear to output the left channel on the low level of dsel output (i 2 s mode). 1dsiz audio data size set to select 32-bit data output format. clear to select 16-bit data output format. 0hlr high/low rate bit set by software when the p ll clock frequency is 384fs. clear by software when the pll clock frequency is 256fs. 76543210 ? ? msreq mudrn - dup1 dup0 auden
65 4173d?usb?02/06 at89c5132 reset value = 1011 0010b table 53. audsta register audsta (s:9ch read only) ? a udio interface status register reset value = 1100 0000b table 54. auddat register auddat (s:9dh) ? audio interface data register bit number bit mnemonic description 7-6 ? reserved the value read from these bits is always 0. do not set these bits. 5 msreq audio sample request flag mask bit set to prevent the sreq flag from generating an audio interrupt. clear to allow the sreq flag to generate an audio interrupt. 4 mudrn audio sample under-run flag mask bit set to prevent the udrn flag from generating an audio interrupt. clear to allow the udrn flag to generate an audio interrupt. 3? reserved the value read from this bit is always 0. do not set this bit. 2-1 dup1:0 audio duplication factor refer to table 50 for bits description. 0 auden audio interface enable bit set to enable the audio interface. clear to disable the audio interface. 76543210 sreq udrn aubusy - - - - - bit number bit mnemonic description 7sreq audio sample request flag set in c51 audio source mode when the audio interface request samples (buffer half empty). this bit generates an interrupt if not masked and if enabled in ien0. cleared by hardware when samples are loaded in auddat. 6 udrn audio sample under-run flag set in c51 audio source mode when the audio interface runs out of samples (buffer empty). this bit generates an interrupt if not masked and if enabled in ien0. cleared by hardware when samples are loaded in auddat. 5 aubusy audio interface busy bit set in c51 audio source mode when the audio interface cannot accept more sample (buffer full). cleared by hardware when buffer is no more full. 4-0 - reserved the value read from these bits is always 0. do not set these bits. 76543210 aud7 aud6 aud5 aud4 aud3 aud2 aud1 aud0
66 4173d?usb?02/06 at89c5132 reset value = 1111 1111b table 55. audclk register audclk (s:ech) ? audio clock divider register reset value = 0000 0000b bit number bit mnemonic description 7-0 aud7:0 audio data 8-bit sampling data for voice or sound playing. 76543210 - - - aucd4 aucd3 aucd2 aucd1 aucd0 bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4-0 aucd4:0 audio clock divider 5-bit divider for audio clock generation.
67 4173d?usb?02/06 at89c5132 15. universal serial bus the at89c5132 implement a usb device controller supporting full-speed data transfer. in addi - tion to the default control endpoint 0, it provides 3 other endpoints, which can be configured in control, bulk, interrup t or isochronous types. this allows to develop firmware conforming to most usb device cla sses, for example the at89c5132 support: ? usb mass storage class control/ bulk/interrupt (cbi) transport, revision 1.0 ? december 14, 1998 ? usb mass storage class bulk-only transport, revision 1.0 ? september 31, 1999 ? usb device firmware upgrade class, revision 1.0 ? may 13, 1999 15.0.1 usb mass storage class cbi transport within the cbi framework, the control endpoint is used to transport command blocks as well as to transport standard usb requests . one bulk out endpoint is used to transport data from the host to the device. one bulk in endpoint is us ed to transport data from the device to the host. and one interrupt endpoint may also be used to si gnal command completion (protocol 0) but it is optional and may not be used (protocol 1). the following at89c5132 configuration adheres to that requirements: ? endpoint 0: 32 bytes, control in-out ? endpoint 1: 64 bytes, bulk out ? endpoint 2: 64 bytes, bulk in ? endpoint 3: 8 bytes, interrupt in 15.0.2 usb mass storage class bulk-only transport within the bulk-only framework, the control endpoin t is only used to transport class-specific and standard usb requests for device set-up and configuration. one bulk-out endpoint is used to transport commands and data from the host to the device. one bulk in endpoint is used to trans - port status and data from the device to the host. no interrupt endpoint is needed. the following at89c5132 configuration adheres to that requirements: ? endpoint 0: 32 bytes, control in-out ? endpoint 1: 64 bytes, bulk out ? endpoint 2: 64 bytes, bulk in ? endpoint 3: not used 15.0.3 usb device firmware upgrade (dfu) the usb device firmware update (dfu) protocol can be used to upgrade the on-chip flash memory of the at89c5132. this allows installing product enh ancements and patc hes to devices that are already in the field. tw o different configurations and desc riptor sets are used to support dfu functions. the run-time co nfiguration co-exist with the us ual functions of the device, which shall be usb mass storage for at89c5132. it is used to initiate dfu from the normal operating mode. the dfu configuration is used to perform the firmware update after device re- configuration and usb reset. it excludes any other function. only the default control pipe (end - point 0) is used to support dfu services in both configurations. the only possible value for the maxpacketsize in th e dfu configuration is 32 bytes, which is the size of the fifo implemented for endpoint 0.
68 4173d?usb?02/06 at89c5132 15.1 description the usb device controller provides the hardwar e that the at89c5132 ne ed to interface a usb link to data flow stored in a double port memory. it requires a 48 mhz reference clock provided by the clock controller as detailed in section "clock controller", page 68 . this clock is used to generate a 12 mhz full speed bit clock from the received usb differential data flow and to transmit data according to full speed usb device tolerance. clock recovery is done by a digital phase locked loop (dpll) block. the serial interface engine (sie) block performs nrzi encoding and decoding, bit stuffing, crc generation and checking, and the serial-parallel data conversion. the universal function interface (ufi) controls th e interface between the data flow and the dual port ram, but also the interf ace with the c51 core itself. figure 15-3 shows how to connect the at89c5132 to the usb connector. d+ and d- pins are connected through 2 termination resistors. a pull- up resistor is implemented on d+ to inform the host of a full speed dev ice connection. value of these resist ors is detailed in the section ?dc characteristics?. figure 15-1. usb device controller block diagram figure 15-2. usb connection 15.1.1 clock controller the usb controller clock is generated by division of the pll clock. the division factor is given by usbcd1:0 bits in u sbclk register (see table 70 ). figure 15-3 shows the usb controller clock usb clock 48 mhz 12 mhz d+ d- dpll sie ufi usb buffer to/from c51 core d+ d- vbus gnd d+ d- vss to p o w e r r usb r usb vdd supply r fs
69 4173d?usb?02/06 at89c5132 generator and its calculation formula. the usb controller clock frequency must always be 48 mhz. figure 15-3. usb clock generator and symbol 15.1.2 serial interface engine (sie) the sie performs the following functions: ? nrzi data encoding and decoding ? bit stuffing and unstuffing ? crc generation and checking ? acks and nacks automatic generation ? token type identifying ? address checking ? clock recovery (using dpll) figure 15-4. sie block diagram usbcd1:0 usbclk 48 mhz usb clock usbclk pllclk usbcd 1 + -------------------------------- = usb clock usb clock symbol pll clock 8 start of packet detector clock recover sync detector pid decoder address decoder serial to parallel converter crc5 & crc16 generator/check usb pattern generator parallel to serial converter bit stuffing nrzi converter crc16 generator nrzi ? nrz bit unstuffing packet bit counter end of packet detector usb clock 48 mhz sysclk data in d+ d- (12 mhz) 8 data out
70 4173d?usb?02/06 at89c5132 15.1.3 function interface unit (ufi) the function interface unit provides the interf ace between the at89c5132 and the sie. it man - ages transactions at the packet level with minima l intervention from the device firmware, which reads and writes the endpoint fifos. figure 15-6 shows typical usb in and out transactions reporting the split in the hardware (ufi) and software (c51) load. figure 15-5. ufi block diagram figure 15-6. usb typical transaction load 15.2 usb interrupt system as shown in figure 15-7 , the usb controller of the at89c5132 handle sixteen interrupt sources. these sources are separated in two groups: th e endpoints interrupts and the controller inter - rupts, combined together to appear as single interrupt source for the c51 core. the usb interrupt is enabled by setting the eusb bit in ien1. to/from c51 core endpoint control c51 side endpoint control usb side endpoint 2 endpoint 1 endpoint 0 usbcon usbint usbien uepint uepien uepnum uepstax usbaddr uepconx uepdatx ueprst ubyctx ufnumh ufnuml asynchronous information transfer control fsm to/from sie 12 mhz dpll out transactions: host ufi c51 out data0 (n bytes) ack endpoint fifo read (n bytes) out data1 nack out data1 ack in transactions: host ufi c51 in ack endpoint fifo write in data1 nack c51 interrupt in data1 c51 interrupt endpoint fifo write
71 4173d?usb?02/06 at89c5132 15.2.1 controller interrupt sources there are four controller interrupt sources which can be enabled separately in usbien: ? spint: suspend interrupt flag. this flag triggers an interrupt when a usb suspend (idle bus for three frame periods: a j state for 3 ms) is detected. ? sofint: start of frame interrupt flag. this flag triggers an interrupt when a usb st art of frame packet has been received. ? eorint: end of reset interrupt flag. this flag triggers an interrupt when a end of reset has been detected by the usb controller. ? wupcpu: wake up cpu interrupt flag. this flag triggers an interrupt when the usb controller is in suspend state and is re- activated by a non-idle signal from usb line. 15.2.2 endpoint interrupt sources each endpoint supports four interrupt sources reported in uepstax and combined together to appear as a single endpoint interrupt source in uepint. each endpoint interrupt can be enabled separately in uepien. ? txcmp: transmitted in data interrupt flag. this flag triggers an interrup t after an in packet has be en transmitted for isochronous endpoints or after it has been accepted (ack?ed) by the host for control, bulk and interrupt endpoints. ? rxout: received out data interrupt flag. this flag triggers an interrupt after a new packet has been received. ? rxsetup: receive setup interrupt flag. this flag triggers an interrupt when a valid setup packet has been received from the host. ? stlcrc: stall sent interrupt fl ag/crc error interrupt flag. this flag triggers an interrupt after a stall handshake has been sent on the bus, for control, bulk and interrupt endpoints. this flag triggers an interrupt when the last data received is corrupted for isochronous endpoints.
72 4173d?usb?02/06 at89c5132 figure 15-7. usb interrupt control block diagram 15.3 registers table 56. usbcon register usbcon (s:bch) ? usb global control register txcmp uepstax.0 rxout uepstax.1 rxsetup uepstax.2 stlcrc uepstax.3 epxie uepien.x epxint uepint.x sofint usbint.3 esofint usbien.3 spint usbint.0 espint usbien.0 eusb ien1.6 eorint usbint.4 wupcpu usbint.5 ewupcpu usbien.5 eeorint usbien.4 endpoint x (x = 0.3) usb interrupt 76543210 usbe suspclk sdrmwup - uprsm rmwupe confg fadden
73 4173d?usb?02/06 at89c5132 reset value = 0000 0000b table 57. usbaddr register usbaddr (s:c6h) ? usb address register bit number bit mnemonic description 7 usbe usb enable bit set to enable the usb controller. clear to disable and reset the usb controller. 6 suspclk suspend usb clock bit set to disable the 48 mhz clock input (resume detection is still active). clear to enable the 48 mhz clock input. 5sdrmwup send remote wake-up bit set to force an external interrupt on the usb controller for remote wake up purpose. an upstream resume is send only if t he bit rmwupe is set, all usb clocks are enabled and the usb bus was in suspend state for at least 5 ms. see uprsm below. cleared by software. 4- reserved the values read from this bit is always 0. do not set this bit. 3 uprsm upstream resume bit (read only) set by hardware when sdrmwup has been set and if rmwupe is enabled. cleared by hardware after the upstream resume has been sent. 2rmwupe remote wake-up enable bit set to enable request an upstream resume signalling to the host. clear after the upstream resume has been indicated by rsminpr. note: do not set this bit if the host has not set the device_remote_wakeup feature for the device. 1confg configuration bit set after a set_configuration request with a non-zero value has been correctly processed. cleared by software when a set_configuration request with a zero value is received. cleared by hardware on hardware reset or when an usb reset is detected on the bus. 0 fadden function address enable bit set by the device firmware after a successful status phase of a set_address transaction. it shall not be cleared afterwards by the device firmware. cleared by hardware on hardware reset or when an usb reset is received. when this bit is cleared, the def ault function address is used (0). 76543210 fen uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0
74 4173d?usb?02/06 at89c5132 reset value = 0000 0000b table 58. usbint register usbint (s:bdh) ? usb global interrupt register reset value = 0000 0000b table 59. usbien register usbien (s:beh) ? usb global interrupt enable register bit number bit mnemonic description 7fen function enable bit set to enable the function. the device firm ware shall set this bit after it has received a usb reset and participate in t he following configuration process with the default address (fen is reset to 0). cleared by hardware at power-up, should not be cleared by the device firmware once set. 6-0 uadd6:0 usb address bits this field contains the default address (0) after power-up or usb bus reset. it shall be written with the value set by a set_address request received by the device firmware. 76543210 - - wupcpu eorint sofint - - spint bit number bit mnemonic description 7 - 6 - reserved the values read from these bits are always 0. do not set these bits. 5 wupcpu wake up cpu interrupt flag set by hardware when the usb controller is in suspend state and is re-activated by a non-idle signal from usb line (not by an upstream resume). this triggers a usb interrupt when ewupcpu is set in the usbien. cleared by software after re-enabling all usb clocks. 4eorint end of reset interrupt flag set by hardware when a end of reset has been detected by the usb controller. this triggers a usb interrupt when eeorint is set in usbien. cleared by software. 3sofint start of frame interrupt flag set by hardware when a usb start of frame packet (sof) has been properly received. this triggers a usb interrupt when esofint is set in usbien. cleared by software. 2 - 1 - reserved the values read from these bits are always 0. do not set these bits. 0 spint suspend interrupt flag set by hardware when a usb suspend (idle bus for three frame periods: a j state for 3 ms) is detected. this triggers a usb in terrupt when espint is set in usbien. cleared by software. 76543210 - - ewupcpu eeorint esofint - - espint
75 4173d?usb?02/06 at89c5132 reset value = 0001 0000b table 60. uepnum register uepnum (s:c7h) ? usb endpoint number reset value = 0000 0000b table 61. uepconx register uepconx (s:d4h) ? usb endpoint x control register (x = epnum set in uepnum) bit number bit mnemonic description 7-6 - reserved the values read from these bits are always 0. do not set these bits. 5 ewupcpu wake up cpu interrupt enable bit set to enable the wake up cpu interrupt. clear to disable the wake up cpu interrupt. 4eeofint end of reset interrupt enable bit set to enable the end of reset interrupt. this bit is set after reset. clear to disable end of reset interrupt. 3esofint start of frame interrupt enable bit set to enable the sof interrupt. clear to disable the sof interrupt. 2-1 - reserved the values read from these bits are always 0. do not set these bits. 0espint suspend interrupt enable bit set to enable suspend interrupt. clear to disable suspend interrupt. 76543210 ------epnum1epnum0 bit number bit mnemonic description 7 - 2 - reserved the values read from these bits are always 0. do not set these bits. 1 - 0 epnum1:0 endpoint number bits set this field with the number of t he endpoint which shall be accessed when reading or writing to registers uepst ax, uepdatx, ubyctlx or uepconx. 76543210 epen - - - dtgl epdir eptype1 eptype0
76 4173d?usb?02/06 at89c5132 reset value = 0000 0000b table 62. uepstax register uepstax (soh) ? usb endpoint x status and cont rol register (x = epnum set in uepnum) bit number bit mnemonic description 7 epen endpoint enable bit set to enable the endpoint according to the device configuration. endpoint 0 shall always be enabled after a hardware or usb bus reset and participate in the device configuration. clear to disable the endpoint according to the device configuration. 6 - 4 - reserved the values read from this bit is always 0. do not set this bit. 3dtgl data toggle status bit (read-only) set by hardware when a data1 packet is received. cleared by hardware when a data0 packet is received. note: when a new data packet is received without dtgl toggling from 1 to 0 or 0 to 1, a packet may have been lost. when this occurs for a bulk endpoint, the device firmware shall consider the host has retried transmitting a properly received packet because the host has not received a valid ack, then the firmware shall discard the new packet (n.b. the endpoint resets to data0 only upon configuration). for interrupt endpoints, data toggling is managed as for bulk endpoints when used. for control endpoints, each setup transaction starts with a data0 and data toggling is then used as for bulk endpoints until the end of the data stage (for a control write transfer); the status stage completes the data transfer with a data1 (for a control read transfer). for isochronous endpoints, the device firm ware shall retrieve every new data packet and may ignore this bit. 2 epdir endpoint direction bit set to configure in direction for bu lk, interrupt and isochronous endpoints. clear to configure out direction for bulk, interrupt and isochronous endpoints. this bit has no effect for control endpoints. 1 - 0 eptype1: 0 endpoint type bits set this field according to the endpoint c onfiguration (endpoint 0 shall always be configured as control): 0 0 control endpoint 0 1 isochronous endpoint 1 0 bulk endpoint 1 1 interrupt endpoint 76543210 dir - stallrq txrdy stlcrc rxsetup rxout txcmp
77 4173d?usb?02/06 at89c5132 reset value = 0000 0000b table 63. ueprst register ueprst (s:d5h) ? usb endpoint fifo reset register bit number bit mnemonic description 7dir control endpoint direction bit this bit is relevant only if the end point is configured in control type. set for the data stage. clear otherwise. note: this bit should be configured on rxsetup interrupt before any other bit is changed. this also determines the status phase (in for a control write and out for a control read). this bit should be cleared for status stage of a control out transaction. 6- reserved the values read from this bits are always 0. do not set this bit. 5 stallrq stall handshake request bit set to send a stall answer to the hos t for the next handshake.clear otherwise. 4 txrdy tx packet ready control bit set after a packet has been written into the endpoint fifo for in data transfers. data shall be written into the endpoint fi fo only after this bit has been cleared. set this bit without writing data to the endpoint fifo to send a zero length packet, which is generally recommended and may be required to terminate a transfer when the length of the last data packet is equal to maxpacketsize (e.g., for control read transfers). cleared by hardware, as soon as t he packet has been sent for isochronous endpoints, or after the host has acknowle dged the packet for control, bulk and interrupt endpoints. 3stlcrc stall sent interrupt flag/crc error interrupt flag for control, bulk and interrupt endpoints: set by hardware after a stall handshake has been sent as requested by stallrq. then, the endpoint interrupt is triggered if enabled in uepien. cleared by hardware when a setup pa cket is received (see rxsetup). for isochronous endpoints: set by hardware if the last data received is corrupted (crc error on data). then, the endpoint interrupt is triggered if enabled in uepien. cleared by hardware when a non corrupted data is received. 2 rxsetup received setup interrupt flag set by hardware when a valid setup pack et has been received from the host. then, all the other bits of the register are cleared by hardware and the endpoint interrupt is triggered if enabled in uepien. clear by software after reading the setup data from the endpoint fifo. 1rxout received out data interrupt flag set by hardware after an out packet has been received. then, the endpoint interrupt is triggered if enabled in uepien and all the following out packets to the endpoint are rejected (nack?ed) until this bit is cleared. however, for control endpoints, an early setup transaction may overwrite the content of the endpoint fifo, even if its data packet is received while this bit is set. clear by software after reading the out data from the endpoint fifo. 0txcmp transmitted in data complete interrupt flag set by hardware after an in packet has been transmitted for isochronous endpoints and after it has been accepted (a ck?ed) by the host for control, bulk and interrupt endpoints. then, the endpoint interrupt is triggered if enabled in uepien. clear by software before setting again txrdy. 76543210 - - - - ep3rst ep2rst ep1rst ep0rst
78 4173d?usb?02/06 at89c5132 reset value = 0000 0000b table 64. uepint register uepint (s:f8h read-only) ? usb endpoint interrupt register reset value = 0000 0000b table 65. uepien register uepien (s:c2h) ? usb endpoint interrupt enable register bit number bit mnemonic description 7 - 4 - reserved the values read from these bits are always 0. do not set these bits. 3 ep3rst endpoint 3 fifo reset set and clear to reset the endpoint 3 fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. 2 ep2rst endpoint 2 fifo reset set and clear to reset the endpoint 2 fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. 1 ep1rst endpoint 1 fifo reset set and clear to reset the endpoint 1 fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. 0 ep0rst endpoint 0 fifo reset set and clear to reset the endpoint 0 fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. 76543210 - - - - ep3int ep2int ep1int ep0int bit number bit mnemonic description 7 - 4 - reserved the values read from these bits are always 0. do not set these bits. 3 ep3int endpoint 3 interrupt flag set by hardware when an interrupt is triggered in uepstax and the endpoint 3 interrupt is enabled in uepien. must be cleared by software. 2 ep2int endpoint 2 interrupt flag set by hardware when an interrupt is triggered in uepstax and the endpoint 2 interrupt is enabled in uepien. must be cleared by software. 1 ep1int endpoint 1 interrupt flag set by hardware when an interrupt is triggered in uepstax and the endpoint 1 interrupt is enabled in uepien. must be cleared by software. 0 ep0int endpoint 0 interrupt flag set by hardware when an interrupt is triggered in uepstax and the endpoint 0 interrupt is enabled in uepien. must be cleared by software. 76543210 - - - - ep3inte ep2inte ep1inte ep0inte
79 4173d?usb?02/06 at89c5132 reset value = 0000 0000b table 66. uepdatx register uepdatx (s:cfh) ? usb endpoint x fifo data regist er (x = epnum set in uepnum) reset value = xxh table 67. ubyctlx register ubyctx (s:e2h) ? usb endpoint x byte co unt register (x = epnum set in uepnum) reset value = 0000 0000b bit number bit mnemonic description 7 - 4 - reserved the values read from these bits are always 0. do not set these bits. 3 ep3inte endpoint 3 interrupt enable bit set to enable the interrupts for endpoint 3. clear to disable the interrupts for endpoint 3. 2 ep2inte endpoint 2 interrupt enable bit set to enable the interrupts for endpoint 2. clear this bit to disable the interrupts for endpoint 2. 1 ep1inte endpoint 1 interrupt enable bit set to enable the interrupts for the endpoint 1. clear to disable the interrupts for the endpoint 1. 0 ep0inte endpoint 0 interrupt enable bit set to enable the interrupts for the endpoint 0. clear to disable the interrupts for the endpoint 0. 76543210 fdat7 fdat6 fdat5 fdat4 fdat3 fdat2 fdat1 fdat0 bit number bit mnemonic description 7 - 0 fdat7:0 endpoint x fifo data data byte to be written to fifo or data byte to be read from the fifo, for the endpoint x (see epnum). 76543210 - byct6 byct5 byct4 byct3 byct2 byct1 byct0 bit number bit mnemonic description 7- reserved the values read from this bits are always 0. do not set this bit. 6-0 byct7:0 byte count byte count of a received data packet. this byte count is equal to the number of data bytes received after the data pid.
80 4173d?usb?02/06 at89c5132 table 68. ufnuml register ufnuml (s:bah, read-only) ? usb frame number low register reset value = 00h table 69. ufnumh register ufnumh (s:bbh, read-only) ? usb frame number high register reset value = 00h table 70. usbclk register usbclk (s:eah) ? usb clock divider register 76543210 fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 bit number bit mnemonic description 7 - 0 fnum7:0 frame number lower 8 bits of the 11-bit frame number. 76543210 - - crcok crcerr - fnum10 fnum9 fnum8 bit number bit mnemonic description 7 - 3 - reserved the values read from these bits ar e always 0. do not set these bits. 5crcok frame number crc ok bit set by hardware after a non corrupted frame number in start of frame packet is received. updated after every start of frame packet reception. note: the start of frame interrupt is generated just after the pid receipt. 4 crcerr frame number crc error bit set by hardware after a corrupted frame number in start of frame packet is received. updated after every start of frame packet reception. note: the start of frame interrupt is generated just after the pid receipt. 3- reserved the values read from this bits ar e always 0. do not set this bit. 2 - 0 fnum10:8 frame number upper 3 bits of the 11-bit frame number. it is provided in the last received sof packet. fnum does not change if a corrupted sof is received. 76543210 ------usbcd1usbcd0 bit number bit mnemonic description 7 - 2 - reserved the values read from these bits are always 0. do not set these bits.
81 4173d?usb?02/06 at89c5132 reset value = 0000 0000b 1 - 0 usbcd1:0 usb controller clock divider 2-bit divider for usb c ontroller clock generation. bit number bit mnemonic description
82 4173d?usb?02/06 at89c5132 16. multimedia card controller the at89c5132 implements a multimedia card (mmc) controller. the mmc is used to store files in removable flash memory cards that can be easily plugged or removed from the application. 16.1 card concept the basic multimedia card concept is based on transferring data via a minimal number of signals. 16.1.1 card signals the communication signals are: ? clk: with each cycle of this signal an one bit transfer on the command and data lines is done. the frequency may vary from zero to the maximum clock frequency. ? cmd: is a bidirectional command channel used for card initialization and data transfer commands. the cmd signal has two operati on modes: open-drain for initialization mode and push-pull for fast command transfer. commands are sent from the multimedia card bus master to the card and responses from the cards to the host. ? dat: is a bidirectional data channel. the dat signal operates in push-pull mode. only one card or the host is driving this signal at a time. 16.1.2 card registers within the card interface five registers are de fined: ocr, cid, csd, rca and dsr. these can be accessed only by corresponding commands. the 32-bit operation conditions register (ocr) stores the v dd voltage profile of the card. the register is optional and can be read only. the 128-bit wide cid register carries the card identification information (card id) used during the card identification procedure. the 128-bit wide card-specific data register (csd ) provides information on how to access the card contents. the csd defines the data forma t, error correction type, maximum data access time, data transfer speed, and whet her the dsr register can be used. the 16-bit relative card address register (rca ) carries the card address assigned by the host during the card identification. this address is used for the addressed host-card communication after the card identification procedure the 16-bit driver stage register (dsr) can be optionally used to improve the bus performance for extended operating conditions (depending on par ameters like bus length, transfer rate or number of cards). 16.2 bus concept the multimedia card bus is designed to connect either solid-state mass-s torage memory or i/o- devices in a card format to mu ltimedia applications. the bus im plementation allows the cover - age of application fields from low-cost systems to systems with a fast data transfer rate. it is a single master bus with a variable number of slaves. the multimedia card bus master is the bus controller and each slave is either a single mass storage card (with possibly different technolo - gies such as rom, otp, flash etc.) or an i/o- card with its own controlling unit (on card) to perform the data transfer. the multimedia card bus also includes power connections to supply the cards.
83 4173d?usb?02/06 at89c5132 the bus communication uses a spec ial protocol (multimedia card bus protocol) which is applica - ble for all devices. therefore, the payload data transfer between the host and the cards can be bidirectional. 16.2.1 bus lines the multimedia card bus architecture requires all cards to be connected to the same set of lines. no card has an individual connection to the host or other devices, which reduces the con - nection costs of the mu ltimedia card system. the bus lines can be divided into three groups: ? power supply: v ss1 and v ss2 , v dd ? used to supply the cards. ? data transfer: mcmd, mdat ? used for bidirectional communication. ? clock: mclk ? used to synchroniz e data transfer across the bus. 16.2.2 bus protocol after a power-on reset, the host must initializ e the cards by a special message-based multime - dia card bus protocol. each message is represented by one of the following tokens: ? command: a command is a token which starts an operation. a command is transferred serially from the host to the card on the mcmd line. ? response: a response is a token which is sent from an addressed card (or all connected cards) to the host as an answer to a previously received command. it is transferred serially on the mcmd line. ? data: data can be transferred from the card to the host or vice-versa. data is transferred serially on the mdat line. card addressing is implemented using a sess ion address assigned during the initialization phase, by the bus controller to all currently connec ted cards. individual cards are identified by their cid number. this method requires that every card will have an unique cid number. to ensure uniqueness of cids the cid register contains 24 bi ts (mid and oid fields) which are defined by the mmca. every card manufacturers is required to apply for an unique mid (and optionally oid) number. multimedia card bus data transfers are composed of these tokens. one data transfer is a bus operation. there are different types of operation s. addressed operations always contain a com - mand and a response token. in addition, some operations have data token, the others transfer their information directly within the command or respon se structure. in this case no data token is present in an operation. the bits on the mdat and the mcmd lines are transferred synchronous to the host clock. two types of data transfer commands are defined: ? sequential commands: these commands initia te a continuous data stream, they are terminated only when a stop command follows on the mcmd line. this mode reduces the command overhead to an absolute minimum. ? block-oriented commands: these commands send data block succeeded by crc bits. both read and write operations allow either single or multiple block transmission. a multiple block transmission is terminated when a stop comm and follows on the mcmd line similarly to the stream read. figure 16-1 to figure 16-5 show the different types of opera tions, on these figures, grayed tokens are from host to card(s) while white tokens are from card(s) to host.
84 4173d?usb?02/06 at89c5132 figure 16-1. sequential read operation figure 16-2. (multiple) block read operation as shown in figure 16-3 and figure 16-4 the data write operation us es a simple busy signalling of the write operation dura tion on the data line (mdat). figure 16-3. sequential write operation figure 16-4. (multiple) block write operation figure 16-5. no response and no data operation data stream command response mcmd mdat data stop operation data transfer operation command response stop command data block mcmd mdat data stop operation block read operation crc multiple block read operation command response command response data block crc data block crc stop command data stream mcmd mdat data stop operation data transfer operation command response command response stop command busy mcmd mdat data stop operation block write operation multiple block write operation busy data block crc data block crc command response command response stop command status busy status command mcmd mdat no data operation no response operation command response
85 4173d?usb?02/06 at89c5132 16.2.3 command token format as shown in figure 16-6 , commands have a fixed code length of 48 bits. each command token is preceded by a start bit: a low level on mcmd line and succeeded by an end bit: a high level on mcmd line. the command content is preceded by a transmission bit: a high level on mcmd line for a command token (host to card) and su cceeded by a 7-bit crc so that transmission errors can be detected and the operation may be repeated. command content contains the command inde x and address information or parameters. figure 16-6. command token format table 71. command token format 16.2.4 response token format there are five types of response tokens (r1 to r5). as shown in figure 16-7 , responses have a code length of 48 bits or 136 bits. a response to ken is preceded by a start bit: a low level on mcmd line and succeeded by an end bit: a high level on mcmd line. the command content is preceded by a transmission bit: a low level on mc md line for a response token (card to host) and succeeded (r1,r2,r4,r5) or not (r3) by a 7-bit crc. response content contains mirrored command and status information (r1 response), cid regis - ter or csd register (r2 response), ocr register (r3 response), or rca register (r4 and r5 response). figure 16-7. response token format 0 total length = 48 bits content crc 1 1 bit position 47 46 45:40 39:8 7:1 0 width (bits) 1163271 value ?0? ?1? - - - ?1? description start bit transmission bit command index argument crc7 end bit 0 total length = 48 bits content crc 0 1 r1, r4, r5 0 total length = 136 bits content = cid or csd crc 0 1 r2 0 total length = 48 bits content 0 1 r3
86 4173d?usb?02/06 at89c5132 table 72. r1 response format (normal response) table 73. r2 response format (cid and csd registers) table 74. r3 response format (ocr register) table 75. r4 response format (fast i/o) table 76. r5 response format 16.2.5 data packet format there are two types of data packets : stream and block. as shown in figure 16-8 , stream data packets have an indeterminate length while block packets have a fixed length depending on the block length. each data packet is preceded by a start bit: a low level on mcmd line and suc - ceeded by an end bit: a high level on mcmd line. due to the fact that there is no predefined end bit position 47 46 45:40 39:8 7:1 0 width (bits) 1163271 value ?0? ?0? - - - ?1? description start bit transmission bit command index card status crc7 end bit bit position 135 134 [133:128] [127:1] 0 width (bits) 116321 value ?0? ?0? ?111111? - ?1? description start bit transmission bit reserved argument end bit bit position 47 46 [45:40] [39:8] [7:1] 0 width (bits) 11 63271 value ?0? ?0? ?111111? - ?1111111? ?1? description start bit transmission bit reserved ocr register reserved end bit bit position 47 46 [45:40] [39:8] [7:1] 0 width (bits) 11 63271 value ?0? ?0? ?100111? - - ?1? description start bit transmission bit command index argument crc7 end bit bit position 47 46 [45:40] [39:8] [7:1] 0 width (bits) 11 63271 value ?0? ?0? ?101000? - - ?1? description start bit transmission bit command index argument crc7 end bit
87 4173d?usb?02/06 at89c5132 in stream packets, crc protection is not included in this case. the crc protection algorithm for block data is a 16-bit ccitt polynomial. figure 16-8. data token format 16.2.6 clock control the mmc bus clock signal can be used by the host to turn the cards into energy saving mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. the host is allowed to lower the clock frequency or shut it down. there are a few restrictions the host must follow: ? the bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency, defined by the cards, a nd the identification frequency defined by the specification document). ? it is an obvious requirement that the clock must be running for the card to output data or response tokens. after the last multimedia card bus transaction, the host is required, to provide 8 (eight) clock cycles for the card to complete the operation before shutting down the clock. following is a list of the various bus transactions: ? a command with no response. 8 clocks after the host command end bit. ? a command with response. 8 clocks after the card command end bit. ? a read data transaction. 8 clocks af ter the end bit of the last data block. ? a write data transaction. 8 clocks after the crc status token. ? the host is allowed to shut down the clock of a ?busy? card. the card will complete the programming operation regardless of the host cl ock. however, the host must provide a clock edge for the card to turn off its busy signal. wi thout a clock edge the card (unless previously disconnected by a deselect command-cmd7) will force th e mdat line down, forever. 16.3 description the mmc controller interfaces to the c51 co re through the following eight special function registers: mmcon0, mmcon1, mmcon2, the th ree mmc control registers (see figure 78 to figure ); mmsta, the mmc status register (see figure 81 ); mmint, the mmc interrupt register (see figure ); mmmsk, the mmc interrupt mask register (see figure 83 ); mmcmd, the mmc com - mand register (see figure 84 ); mmdat, the mmc data register (see figure ); and mmclk, the mmc clock register (see figure 86 ). as shown in figure 16-9 , the mmc controller is divided in four blocks: the clock generator that handles the mclk (formally the mmc clk) output to the card, the command line controller that handles the mcmd (formally the mmc cmd) line traffic to or from the card, the data line control - ler that handles the mdat (formally the mmc da t) line traffic to or from the card, and the interrupt controller that handles the mmc controlle r interrupt sources. these blocks are detailed in the followi ng sections. 0 content 1 sequential data crc block data 0 content 1 block length
88 4173d?usb?02/06 at89c5132 figure 16-9. mmc controller block diagram 16.4 clock generator the mmc clock is generated by di vision of the oscillator clock (f osc ) issued from the clock con - troller block as detailed in section "oscillator", page 12 . the division factor is given by mmcd7:0 bits in mmclk register. figure 16-10 shows the mmc clock generat or and its output clock cal - culation formula. figure 16-10. mmc clock generator and symbol as soon as mmcen bit in mmcon2 is set, the mmc controller receives its system clock. the mmc command and data clock is generated on mc lk output and sent to the command line and data line controllers. figure 16-11 shows the mmc controller configuration flow. as exposed in section ?clock control? , mmcd7:0 bits can be used to dynamically increase or reduce the mmc clock. figure 16-11. configuration flow 16.5 command line controller as shown in figure 16-12 , the command line controller is divi ded in two channels: the command transmitter channel that handles the command tr ansmission to the card through the mcmd line and the command receiver channel that handles the response reception from the card through the mcmd line. these channels are detailed in the following sections. osc clock mcmd mclk 8 internal bus mdat command line clock mmc interrupt request generator controller data line controller interrupt controller mmcd7:0 mmclk mmc clock mmcclk oscclk mmcd 1 + ----------------------------- = osc clock mmcen mmcon2.7 controller clock mmc clock mmc clock symbol mmc controller configuration configure mmc clock mmclk = xxh mmcen = 1 flowc = 0
89 4173d?usb?02/06 at89c5132 figure 16-12. command line controller block diagram 16.5.1 command transmitter to send a command to the card, the user must load the command index (1 byte) and argument (4 bytes) in the command transmit fifo using the mmcmd register. before starting transmis - sion by setting and clearing the cmden bit in mmcon1 register, the user must first configure: ? respen bit in mmcon1 regist er to indicate whether a re sponse is expe cted or not. ? rfmt bit in mmcon0 register to indi cate the response size expected. ? crcdis bit in mmcon0 register to indicate whether the crc7 include d in the response will be computed or not. in order to avoid crc er ror, crcdis may be set for responses that do not include crc7. figure 16-13 summarizes the command transmission flow. as soon as command transmission is enabled, the cflck flag in mmsta is set indicating that write to the fifo is locked . this mechanism is implemented to avoid command over-run. the end of the command transmission is signalled by the eoci flag in mmint register becoming set. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 96 . the end of the command transmission also resets the cflck flag. the user may abort command loading by setting and clearing the ctptr bit in mmcon0 regis - ter which resets th e write pointer to the transmit fifo. ctptr mmcon0.4 crptr mmcon0.5 mcmd cmden mmcon1.0 tx command line finished state machine data converter // -> serial 5-byte fifo mmcmd tx pointer rfmt mmcon0.1 crcdis mmcon0.0 respen mmcon1.1 data converter serial -> // rx pointer 17-byte fifo mmcmd cflck mmsta.0 crc7 generator rx command line finished state machine crc7 and format checker crc7s mmsta.2 respfs mmsta.1 eoci mmint.5 eori mmint.6 command transmitter command receiver write read
90 4173d?usb?02/06 at89c5132 figure 16-13. command transmission flow 16.5.2 command receiver the end of the response reception is signalled by the eori flag in mmint register. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 96 . when this flag is set, two other flags in mmsta register: respfs and crc7s give a status on the response received. respfs indicates if the response format is correct or not: the size is the one expected (48 bits or 136 bits) and a valid end bit has been received, and crc7s indicates if the crc7 computation is correct or not. these flags are cleared when a command is sent to the card and updated when the response has been received. the user may abort response reading by setting and clearing the crptr bit in mmcon0 regis - ter which resets th e read pointer to the receive fifo. according to the mmc specification dela y between a command and a response (formally n cr parameter) cannot exceed 64 mmc clock periods . to avoid any locking of the mmc controller when card does not send its response (e.g. phys ically removed from the bus), user must launch a timeout period to exit from such situation. in case of timeout user may reset the command con - troller and its internal state machine by setti ng and clearing the ccr bit in mmcon2 register. this timeout may be disarmed when receiving the response. 16.6 data line controller the data line controller is based on a 16-byte fifo used both by the data transmitter channel and by the data receiver channel. command transmission load command in buffer mmcmd = index mmcmd = argument configure response respen = x rfmt = x crcdis = x transmit command cmden = 1 cmden = 0
91 4173d?usb?02/06 at89c5132 figure 16-14. data line controller block diagram 16.6.1 fifo implementation the 16-byte fifo is based on a dual 8-byte fifo managed using two pointers and four flags indicating the status full and empty of each fifo. pointers are not accessible to user but can be reset at any time by setting and clearing drptr and dtptr bits in mmcon0 register. resetting the pointers is equivalent to abort the writing or reading of data. f1ei and f2ei flags in mmint register signal when set that respectively fifo1 and fifo2 are empty. f1fi and f2fi flags in mmint register signal when set that respectively fifo1 and fifo2 are full. these flags may generate an mmc interrupt request as detailed in section ?interrupt? . 16.6.2 data configuration before sending or receiving any data, the data li ne controller must be configured according to the type of the data transfer considered. this is achieved using the data format bit: dfmt in mmcon0 register. clearin g dfmt bit enables the data stream format while setting dfmt bit enables the data block format. in data block format , user must also configure the single or multi- block mode by clearing or setting the mblock bit in mmcon0 register and the block length using blen3:0 bits in mmcon1 according to table 77 . figure 16-15 summarizes the data modes configuration flows. table 77. block length programming mcbi mmint.1 datfs mmsta.3 crc16s mmsta.4 f2fi mmint.3 f2ei mmint.1 dfmt mmcon0.2 mblock mmcon0.3 datdir mmcon1.3 data converter // -> serial blen3:0 mmcon1.7:4 daten mmcon1.2 data line finished state machine data converter serial -> // dtptr mmcon0.6 drptr mmcon0.7 tx pointer rx pointer 8-byte fifo 1 8-byte fifo 2 16-byte fifo mmdat f1ei mmint.0 crc16 and format checker f1fi mmint.2 eofi mmint.4 cbusy mmsta.5 crc16 generator mdat blen3:0 block length (byte) blen = 0000 to 1011 length = 2 blen : 1 to 2048 > 1011 reserved: do not program blen3:0 > 1011
92 4173d?usb?02/06 at89c5132 figure 16-15. data controller configuration flows 16.6.3 data transmitter 16.6.3.1 configuration for transmitting data to the card, user must fi rst configure the data controller in transmission mode by setting the datdir bit in mmcon1 register. figure 16-16 summarizes the data stream transmission flows in both polling and interrupt modes while figure 16-17 summarizes the data block transmissio n flows in both polling and interrupt modes, these flows assume that block length is greater than 16 data. 16.6.3.2 data loading data is loaded in the fifo by writing to mmdat register. number of data loaded may vary from 1 to 16 bytes. then if necessary (more than 16 bytes to send) user must wait that one fifo becomes empty (f1ei or f2ei set) before loading 8 new data. 16.6.3.3 data transmission transmission is enabled by setting and clearing daten bit in mmcon1 register. data is transmitted imme diately if the response has already been received, or is delayed after the response reception if its status is correct. in both cases transmission is delayed if a card sends a busy state on the data line until the end of this busy condition. according to the mmc specificat ion, the data transfer from the host to the card may not start sooner than 2 mmc clock periods after t he card response was received (formally n wr parame - ter). to address all card types, this delay can be programmed using datd1:0 bits in mmcon2 register from 3 mmc clock periods when datd1: 0 bits are cleared to 9 mmc clock periods when datd2:0 bits are set, by step of 2 mmc clock periods. 16.6.3.4 end of transmission the end of data frame (block or stream) transmi ssion is signalled by the eofi flag in mmint register. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 96 . in data stream mode, eofi flag is set, after re ception of the end bit. this assumes user has pre - viously sent the stop command to the card, whic h is the only way to stop stream transfer. in data block mode, eofi flag is set, a fter reception of the crc status token (see figure 16-4 ). two other flags in mmsta register: datfs and crc16s report a status on the frame sent. datfs indicates if the crc status token format is correct or not, and crc16s indicates if the card has found the crc16 of the block correct or not. data single block configuration data stream configuration configure format dfmt = 0 data multi-block configuration configure format dfmt = 1 mblock = 1 blen3:0 = xxxxb configure format dfmt = 1 mblock = 0 blen3:0 = xxxxb
93 4173d?usb?02/06 at89c5132 16.6.3.5 busy status as shown in figure 16-4 the card uses a busy token during a block write operation. this busy status is reported by the cbusy flag in mmst a register and by the mcbi flag in mmint which is set every time cbusy toggles, i.e. when the ca rd enters and exits its busy state. this flag may generate an mmc interr upt request as detailed in section "interrupt", page 96 . figure 16-16. data stream transmission flows send stop command data stream transmission start transmission daten = 1 daten = 0 fifo empty? f1ei or f2ei = 1? fifo filling write 8 data to mmdat no more data to send? fifos filling write 16 data to mmdat a. polling mode data stream initialization fifos filling write 16 data to mmdat data stream transmission isr fifo filling write 8 data to mmdat send stop command no more data to send? b. interrupt mode fifo empty? f1ei or f2ei = 1? start transmission daten = 1 daten = 0 unmask fifos empty f1em = 0 f2em = 0 mask fifos empty f1em = 1 f2em = 1
94 4173d?usb?02/06 at89c5132 figure 16-17. data block transmission flows 16.6.4 data receiver 16.6.4.1 configuration to receive data from the card, the user must fi rst configure the data controller in reception mode by clearing the datdir bit in mmcon1 register. figure 16-18 summarizes the data stream reception flows in both polling and interrupt modes while figure 16-19 summarizes the data block reception flows in both polling and interrupt modes, these flows assume that block length is greater than 16 bytes. 16.6.4.2 data reception the end of data frame (block or stream) receptio n is signalled by the eofi flag in mmint regis - ter. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 96 . when this flag is set, two other flags in mmsta register: datfs and crc16s give a status on the frame received. datfs indicates if the fram e format is correct or not: a valid end bit has been received, and crc16s indicates if the crc 16 computation is correct or not. in case of data stream crc16s has no meaning and stays cleared. according to the mmc specification data transmiss ion, the card starts after the access time delay (formally n ac parameter) beginning from the end bit of the read command. to avoid any locking of the mmc cont roller when card does not send its data (e.g. physically removed from the bus), the user must launch a ti me-out period to exit from such situation. in case of time-out data block transmission start transmission daten = 1 daten = 0 fifo empty? f1ei or f2ei = 1? fifo filling write 8 data to mmdat no more data to send? fifos filling write 16 data to mmdat a. polling mode data block initialization start transmission daten = 1 daten = 0 fifos filling write 16 data to mmdat data block transmission isr fifo filling write 8 data to mmdat no more data to send? b. interrupt mode fifo empty? f1ei or f2ei = 1? mask fifos empty f1em = 1 f2em = 1 unmask fifos empty f1em = 0 f2em = 0
95 4173d?usb?02/06 at89c5132 the user may reset the dat a controller and its inter nal state machine by se tting and clearing the dcr bit in mmcon2 register. this time-out may be disarmed after receiving 8 data (f1fi flag set) or after receiving end of frame (eofi flag set) in case of block length less than 8 data (1, 2 or 4). 16.6.4.3 data reading data is read from the fifo by reading to mm dat register. each time one fifo becomes full (f1fi or f2fi set), user is requested to flush this fifo by reading 8 data. figure 16-18. data stream reception flows data stream reception fifo full? f1fi or f2fi = 1? fifo reading read 8 data from mmdat no more data to receive? a. polling mode data stream initialization data stream reception isr fifo reading read 8 data from mmdat send stop command no more data to receive? b. interrupt mode fifo full? f1fi or f2fi = 1? unmask fifos full f1fm = 0 f2fm = 0 send stop command mask fifos full f1fm = 1 f2fm = 1
96 4173d?usb?02/06 at89c5132 figure 16-19. data block reception flows 16.6.5 flow control to allow transfer at high speed without taking care of cpu os cillator frequency, the flowc bit in mmcon2 allows control of the data flow in both transmission and reception. during transmission, setting the fl owc bit has the following effects: ? mmclk is stopped when both fifos become empty: f1ei and f2ei set. ? mmclk is restarted when one of the fifos becomes full: f1ei or f2ei cleared. during reception, setting the flowc bit has the following effects: ? mmclk is stopped when both fifos become full: f1fi and f2fi set. ? mmclk is restarted when one of the fifos becomes empty: f1fi or f2fi cleared. as soon as the clock is stopped, the mmc bus is fr ozen and remains in its state until the clock is restored by writing or reading data in mmdat. 16.7 interrupt 16.7.1 description as shown in figure 16-20 , the mmc controller implements eight interrupt sources reported in mcbi, eori, eoci, eofi, f2fi, f1fi, and f2ei flags in mmcint register. these flags were detailed in the previous sections. all of these sources are maskable separat ely using mcbm, eorm, eocm, eofm, f2fm, f1fm, and f2em mask bits, resp ectively, in mmmsk register. data block reception start transmission daten = 1 daten = 0 fifo full? f1ei or f2ei = 1? fifo reading read 8 data from mmdat no more data to receive? a. polling mode data block initialization start transmission daten = 1 daten = 0 data block reception isr fifo reading read 8 data from mmdat no more data to receive? b. interrupt mode fifo full? f1ei or f2ei = 1? mask fifos full f1fm = 1 f2fm = 1 unmask fifos full f1fm = 0 f2fm = 0
97 4173d?usb?02/06 at89c5132 the interrupt request is generated each time an unmasked flag is set, and the global mmc con - troller interrupt enable bit is set (emmc in ien1 register). reading the mmint register automatically clears the interrupt flags (acknowledgment). this implies that register content must be saved and te sted interrupt flag by interrupt flag to be sure not to overlook any interrupts. figure 16-20. mmc controller interrupt system 16.8 registers table 78. mmcon0 register mmcon0 (s:e4h) ? mmc control register 0 mmc interface interrupt request mcbi mmint.7 eocm mmmsk.5 emmc ien1.0 mcbm mmmsk.7 eorm mmmsk.6 eofi mmint.4 f2fm mmmsk.3 eofm mmmsk.4 eori mmint.6 f2fi mmint.3 eoci mmint.5 f2em mmmsk.1 f1fm mmmsk.2 f1ei mmint.0 f1em mmmsk.0 f1fi mmint.2 f2ei mmint.1 76543210 drptr dtptr crptr ctptr mblock dfmt rfmt crcdis bit number bit mnemonic description 7drptr data receive pointer reset bit set to reset the read pointer of the data fifo. clear to release the read pointer of the data fifo.
98 4173d?usb?02/06 at89c5132 reset value = 0000 0000b table 79. mmcon1 register mmcon1 (s:e5h) ? mmc control register 1 reset value = 0000 0000b table 80. mmcon2 register 6 dtptr data transmit pointer reset bit set to reset the write pointer of the data fifo. clear to release the write pointer of the data fifo. 5crptr command receive pointer reset bit set to reset the read pointer of the receive command fifo. clear to release the read pointer of the receive command fifo. 4 ctptr command transmit pointer reset bit set to reset the write pointer of the transmit command fifo. clear to release the read pointer of the transmit command fifo. 3mblock multi-block enable bit set to select multi-block data format. clear to select single block data format. 2dfmt data format bit set to select the block-oriented data format. clear to select the stream data format. 1rfmt response format bit set to select the 48-bit response format. clear to select the 136-bit response format. 0 crcdis crc7 disable bit set to disable the crc7 computation when receiving a response. clear to enable the crc7 computation when receiving a response. 76543210 blen3 blen2 blen1 blen0 datdir daten respen cmden bit number bit mnemonic description 7 - 4 blen3:0 block length bits refer to table 77 for bits description. do not program value > 1011b. 3datdir data direction bit set to select data transfer from host to card (write mode). clear to select data transfer from card to host (read mode). 2daten data transmission enable bit set and clear to enable data transmission immediately or after response has been received. 1 respen response enable bit set and clear to enable the reception of a response following a command transmission. 0cmden command transmission enable bit set and clear to enable transmission of the command fifo to the card. bit number bit mnemonic description
99 4173d?usb?02/06 at89c5132 mmcon2 (s:e6h) ? mmc control register 2 reset value = 0000 0000b table 81. mmsta register mmsta (s:deh read only) ? mm c control and status register 76543210 mmcen dcr ccr - - datd1 datd0 flowc bit number bit mnemonic description 7 mmcen mmc clock enable bit set to enable the mclk clocks and activate the mmc controller. clear to disable the mmc clocks and freeze the mmc controller. 6dcr data controller reset bit set and clear to reset the data line controller in case of transfer abort. 5ccr command controller reset bit set and clear to reset the command line controller in case of transfer abort. 4 - 3 - reserved the values read from these bits are always 0. do not set these bits. 2 - 1 datd1:0 data transmission delay bits used to delay the data transmission afte r a response from 3 mmc clock periods (all bits cleared) to 9 mmc clock periods (all bits set) by step of 2 mmc clock periods. 0flowc mmc flow control bit set to enable the flow control during data transfers. clear to disable the flow control during data transfers. 76543210 - - cbusy crc16s datfs crc7s respfs cflck bit number bit mnemonic description 7 - 6 - reserved the values read from these bits are always 0. do not set these bits. 5 cbusy card busy flag set by hardware when the card sends a busy state on the data line. cleared by hardware when the card no more sends a busy state on the data line.
100 4173d?usb?02/06 at89c5132 reset value = 0000 0000b table 82. mmint register mmint (s:e7h read only) ? mmc interrupt register 4 crc16s crc16 status bit transmission mode set by hardware when the token response reports a good crc. cleared by hardware when the token response reports a bad crc. reception mode set by hardware when the crc16 received in the data block is correct. cleared by hardware when the crc16 received in the data block is not correct. 3datfs data format status bit transmission mode set by hardware when the format of the token response is correct. cleared by hardware when the format of the token response is not correct. reception mode set by hardware when the format of the frame is correct. cleared by hardware when the format of the frame is not correct. 2 crc7s crc7 status bit set by hardware when the crc7 computed in the response is correct. cleared by hardware when the crc7 computed in the response is not correct. this bit is not relevant when crcdis is set. 1 respfs response format status bit set by hardware when the format of a response is correct. cleared by hardware when the format of a response is not correct. 0cflck command fifo lock bit set by hardware to signal user not to write in the transmit command fifo: busy state. cleared by hardware to signal user the tr ansmit command fifo is available: idle state. 76543210 mcbi eori eoci eofi f2fi f1fi f2ei f1ei bit number bit mnemonic description 7mcbi mmc card busy interrupt flag set by hardware when the card enters or exits its busy state (when the busy signal is asserted or deasserted on the data line). cleared when reading mmint. bit number bit mnemonic description
101 4173d?usb?02/06 at89c5132 reset value = 0000 0011b table 83. mmmsk register mmmsk (s:dfh) ? mmc interrupt mask register 6eori end of response interrupt flag set by hardware at the end of response reception. cleared when reading mmint. 5eoci end of command interrupt flag set by hardware at the end of command transmission. clear when reading mmint. 4eofi end of frame interrupt flag set by hardware at the end of frame (stream or block) transfer. clear when reading mmint. 3f2fi fifo 2 full interrupt flag set by hardware when second fifo becomes full. cleared by hardware when second fifo becomes empty. 2f1fi fifo 1 full interrupt flag set by hardware when first fifo becomes full. cleared by hardware when first fifo becomes empty. 1f2ei fifo 2 empty interrupt flag set by hardware when second fifo becomes empty. cleared by hardware when second fifo becomes full. 0f1ei fifo 1 empty interrupt flag set by hardware when first fifo becomes empty. cleared by hardware when first fifo becomes full. 76543210 mcbm eorm eocm eofm f2fm f1fm f2em f1em bit number bit mnemonic description 7mcbm mmc card busy interrupt mask bit set to prevent mcbi flag from generating an mmc interrupt. clear to allow mcbi flag to generate an mmc interrupt. 6eorm end of response interrupt mask bit set to prevent eori flag from generating an mmc interrupt. clear to allow eori flag to generate an mmc interrupt. 5eocm end of command interrupt mask bit set to prevent eoci flag from generating an mmc interrupt. clear to allow eoci flag to generate an mmc interrupt. 4eofm end of frame interrupt mask bit set to prevent eofi flag from generating an mmc interrupt. clear to allow eofi flag to generate an mmc interrupt. 3f2fm fifo 2 full interrupt mask bit set to prevent f2fi flag from generating an mmc interrupt. clear to allow f2fi flag to generate an mmc interrupt. bit number bit mnemonic description
102 4173d?usb?02/06 at89c5132 reset value = 1111 1111b table 84. mmcmd register mmcmd (s:ddh) ? mmc command register reset value = 1111 1111b 2f1fm fifo 1 full interrupt mask bit set to prevent f1fi flag from generating an mmc interrupt. clear to allow f1fi flag to generate an mmc interrupt. 1f2em fifo 2 empty interrupt mask bit set to prevent f2ei flag from generating an mmc interrupt. clear to allow f2ei flag to generate an mmc interrupt. 0f1em fifo 1 empty interrupt mask bit set to prevent f1ei flag from generating an mmc interrupt. clear to allow f1ei flag to generate an mmc interrupt. 76543210 mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 bit number bit mnemonic description 7 - 0 mc7:0 mmc command receive byte output (read) register of the response fifo. mmc command transmit byte input (write) register of the command fifo. bit number bit mnemonic description
103 4173d?usb?02/06 at89c5132 table 85. mmdat register mmdat (s:dch) ? mmc data register reset value = 1111 1111b table 86. mmclk register mmclk (s:edh) ? mmc clock divider register reset value = 0000 0000b 76543210 md7 md6 md5 md4 md3 md2 md1 md0 bit number bit mnemonic description 7 - 0 md7:0 mmc data byte input (write) or output (read) register of the data fifo. 76543210 mmcd7 mmcd6 mmcd5 mmcd4 mmcd3 mmcd2 mmcd1 mmcd0 bit number bit mnemonic description 7 - 0 mmcd7:0 mmc clock divider 8-bit divider for mmc clock generation.
104 4173d?usb?02/06 at89c5132 17. ide/atapi interface the at89c5132 provide an ide/atapi interface allowing connection of devices such as cd- rom reader, compactflash cards, har d disk drive, etc. it consists of a 16-bit data transfer (read or write) between the at89c5132 and the ide devices. 17.1 description the ide interface mode is enabled by setting the ext16 bit in auxr (see table 14 on page 27 ). as soon as this bit is set, all movx instructions read or write are done in a 16-bit mode compare to the standard 8-bit mode. p0 carries the low order multiplexed address and data bus (a7:0, d7:0) while p2 carries the high order multiplexed address and data bus (a15:8, d15:8). when writing data in ide mode, the acc contains d7:0 data (as in 8-bit mode) while dat16h register (see table 88 ) contains d15:8 data. when reading data in ide mode, d7:0 data is returned in acc while d15:8 data is returned in dat16h. figure 17-1 shows the ide read bus cycle while figure 17-2 shows the ide write bus cycle. for simplicity, these figures depict the bus cycle wave forms in idealized form and do not provide pre - cise timing information. for ide bus cycle timing parameters refer to the section ?ac characteristics?. ide cycle takes 6 cpu clock periods which is equi valent to 12 oscillator clock periods in stan - dard mode or 6 oscillator clock pe riods in x2 mode. for further in formation on x2 mode, re fer to the section ?x2 feature?, page 12 . slow ide devices can be accessed by stretching the read and write cycles . this is done using the m0 bit in auxr. setting th is bit changes the width of the rd and wr signals from 3 to 15 cpu clock periods. figure 17-1. ide read waveforms notes: 1. rd signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. 3. when executing movx @dptr instruction, if dphdis is set (page a ccess mode), p2 out - puts sfr content instead of dph. ale p0 p2 rd (1) dpl or ri d7:0 p2 cpu clock dph or p2 (2),(3) d15:8 p2
105 4173d?usb?02/06 at89c5132 figure 17-2. ide write waveforms notes: 1. wr signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. 3. when executing movx @dptr instruction, if dphdis is set (page a ccess mode), p2 out - puts sfr content instead of dph. 17.1.1 ide device connection figure 17-3 and figure 17-4 show two examples on how to in terface up to two ide devices to the at89c5132. in both examples p0 carries ide low order data bits d7:0, p2 carries ide high order data bits d15:8, while rd and wr signals are respectively c onnected to the ide nior and niow signals. other ide cont rol signals are generated by the ex ternal address latch outputs in the first example while they are generated by some port i/os in the second one. using an exter - nal latch will achieve higher transfer rate. figure 17-3. ide device connection example 1 figure 17-4. ide device connection example 2 ale p0 p2 wr (1) dpl or ri d7:0 p2 cpu clock dph or p2 (2),(3) d15:8 p2 p2 p0 d15-8 a2:0 ale niow nior rd wr d7:0 ncs1:0 nreset d15-8 a2:0 niow nior d7:0 ncs1:0 nreset latch ide device 0 ide device 1 at89c5132 px.y p2/a15:8 p0/ad7:0 d15-8 a2:0 p4.5 niow nior rd wr d7:0 ncs1:0 nreset d15-8 a2:0 niow nior d7:0 ncs1:0 nreset p4.2:0 p4.4:3 ide device 0 at89c5132 ide device 1
106 4173d?usb?02/06 at89c5132 table 87. external data memory interface signals 17.2 registers table 88. dat16h register dat16h (s:f9h) ? data 16 high order byte reset value = 0000 0000b signal name type description alternate function a15:8 i/o address lines upper address lines for the external bus. multiplexed higher address and data lines for the ide interface. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address and data lines for the ide interface. p0.7:0 ale o address latch enable ale signals indicates that valid address information is available on lines ad7:0. - rd o read read signal output to external data memory. p3.7 wr o write write signal output to external memory. p3.6 76543210 d15 d14 d13 d12 d11 d10 d9 d8 bit number bit mnemonic description 7 - 0 d15:8 data 16 high order byte when ext16 bit is set, dat16h is set by softwa re with the high order data byte prior any movx write instruction. when ext16 bit is set, dat16h contains the high order data byte after any movx read instruction.
107 4173d?usb?02/06 at89c5132 18. serial i/o port the serial i/o port in the at89c5132 provides both synchronous and asynchronous communi - cation modes. it operates as a synchronous receiver and transmitter in one single mode (mode 0) and operates as an universal asynchr onous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous modes support framing error detection and multiprocessor communication with automatic address recognition. 18.1 mode selection sm0 and sm1 bits in scon register (see figure 91 ) are used to select a mode among the sin - gle synchronous and the three asynchronous modes according to table 89 . table 89. serial i/o port mode selection 18.2 baud rate generator depending on the mode and the source selection, the baud rate can be generated from either the timer 1 or the internal baud rate generator. the timer 1 can be used in modes 1 and 3 while the internal baud rate generator can be used in modes 0, 1 and 3. the addition of the internal baud rate generator allows freeing of the timer 1 for other pur - poses in the application. it is hi ghly recommended to use the internal baud rate generator as it allows higher and more accurate baud rates than timer 1. baud rate formulas depend on the modes select ed and are given in the following mode sections. 18.2.1 timer 1 when using timer 1, the baud rate is derived fr om the overflow of t he timer. as shown in figure 18-1 timer 1 is used in its 8-bit auto-reload mode (detailed in section "mode 2 (8-bit timer with auto-reload)", page 51 ). smod1 bit in pcon register allows doubling of the gener - ated baud rate. sm0 sm1 mode description baud rate 0 0 0 synchronous shift register fixed/variable 0 1 1 8-bit uart variable 10 29-bit uart fixed 1 1 3 9-bit uart variable
108 4173d?usb?02/06 at89c5132 figure 18-1. timer 1 baud rate generator block diagram 18.2.2 internal baud rate generator when using the internal baud rate generator, the baud rate is derived from the overflow of the timer. as shown in figure 18-2 , the internal baud rate generator is an 8-bit auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6 depending on the spd bit in bdrcon register (see table 95 ). the internal baud rate generator is enabled by setting bbr bit in bdrcon register. smod1 bit in pcon register allows doubling of the generated baud rate. figure 18-2. internal baud rate generator block diagram 18.3 synchronous mode (mode 0) mode 0 is a half-duplex, synchronous mode, whic h is commonly used to expand the i/0 capabil - ities of a device with shift registers. the transmit data (txd) pin outputs a set of eight clock pulses while the receive data (rxd) pin transmits or receives a byte of data. the 8-bit data are transmitted and received least-significant bit (lsb) first. shifts occur at a fixed baud rate (see section "baud rate selection (mode 0)", page 110 ). figure 18-3 shows the serial port block dia - gram in mode 0. tr1 tcon.6 0 1 gate1 tmod.7 overflow c/t1# tmod.6 tl1 (8 bits) th1 (8 bits) int1 t1 per clock 6 0 1 smod1 pcon.7 2 t1 clock to serial port 0 1 overflow spd bdrcon.1 brg (8 bits) brl (8 bits) per clock 6 ibrg clock brr bdrcon.4 0 1 smod1 pcon.7 2 to serial port ibrg0 clock to serial port (m0)
109 4173d?usb?02/06 at89c5132 figure 18-3. serial i/o port block diagram (mode 0) 18.3.1 transmission (mode 0) to start a transmission mode 0, write to scon register clearing bits sm0, sm1. as shown in figure 18-4 , writing the byte to transmit to sb uf register starts the transmission. hardware shifts the lsb (d0) onto the rxd pin during the first clock cycle composed of a high level then low level signal on txd. during the ei ghth clock cycle the msb (d7) is on the rxd pin. then, hardware drives the rxd pin high and asserts ti to indicate the end of the transmission. figure 18-4. transmission waveforms (mode 0) 18.3.2 reception (mode 0) to start a reception in mode 0, write to scon register clearing sm0, sm1 and ri bits and set - ting the ren bit. as shown in figure 18-5 , clock is pulsed and the lsb (d0) is sampled on the rxd pin. the d0 bit is then shifted into the shift register. after ei ght sampling, the msb (d7) is shifted into the shift register, and hardware asserts ri bit to indicate a completed reception. software can then read the received byte from sbuf register. txd rxd sbuf tx sr sbuf rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 mode controller ri scon.0 ti scon.1 baud rate controller write to sbuf txd rxd ti d0 d1 d2 d3 d4 d5 d6 d7
110 4173d?usb?02/06 at89c5132 figure 18-5. reception waveforms (mode 0) 18.3.3 baud ra te selection (mode 0) in mode 0, the baud rate can be either fixed or variable. as shown in figure 18-6 , the selection is done using m0src bit in bdrcon register. figure 18-7 gives the baud rate calculation formulas for each baud rate source. figure 18-6. baud rate source selection (mode 0) figure 18-7. baud rate formulas (mode 0) write to scon txd rxd ri d0 d1 d2 d3 d4 d5 d6 d7 set ren, clear ri 0 1 m0src bdrcon.0 per clock 6 to ibrg0 clock serial port baud_rate= 6 (1-spd) ? 16 ? (256 -brl) f per brl= 256 - 6 (1-spd) ? 16 ? baud_rate f per a. fixed formula b. variable formula baud_rate = 6 f per
111 4173d?usb?02/06 at89c5132 18.4 asynchronous modes (modes 1, 2 and 3) the serial port has one 8-bit and two 9- bit asynchronous modes of operation. figure 18-8 shows the serial port block diagram in asynchronous modes. figure 18-8. serial i/o port block diagram (modes 1, 2 and 3) 18.4.0.1 mode 1 mode 1 is a full-duplex, asynchr onous mode. the data frame (see figure 18-9 ) consists of 10 bits: one start, eight data bits and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. when data is received, the stop bit is read in the rb8 bit in scon register. figure 18-9. data frame format (mode 1) 18.4.0.2 modes 2 and 3 modes 2 and 3 are full-duplex, asyn chronous modes. the data frame (see figure 18-10 ) con - sists of 11 bits: one start bit, eight data bi ts (transmitted and received lsb first), one programmable ninth data bit and one stop bit. se rial data is transmitted on the txd pin and received on the rxd pin. on receive, the ninth bit is read from rb8 bit in scon register. on transmit, the ninth data bit is wr itten to tb8 bit in scon register . alternatively, the ninth bit can be used as a command/data flag. figure 18-10. data frame format (modes 2 and 3) 18.4.1 transmission (modes 1, 2 and 3) to initiate a transmission, write to scon r egister, setting sm0 and sm1 bits according to table 89 , and setting the ninth bit by writing to tb8 bit. then, writing the byte to be transmitted to sbuf register starts the transmission. tb8 scon.3 ibrg clock rxd txd sbuf tx sr rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 ri scon.0 ti scon.1 mode & clock controller sbuf rx rb8 scon.2 sm2 scon.4 t1 clock per clock mode 1 d0 d1 d2 d3 d4 d5 d6 d7 start bit 8-bit data stop bit d0 d1 d2 d3 d4 d5 d6 d8 start bit 9-bit data stop bit d7
112 4173d?usb?02/06 at89c5132 18.4.2 reception (modes 1, 2 and 3) to prepare for reception, write to scon regi ster, setting sm0 and sm1 bits according to table 89 , and set the ren bit. the actual reception is then initiated by a detected high-to-low transition on the rxd pin. 18.4.3 framing error detection (modes 1, 2 and 3) framing error detection is provided for the three asynchronous modes. to enable the framing bit error detection feature, set smod0 bi t in pcon register as shown in figure 18-11 . when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two devices. if a valid stop bit is not found, the software sets fe bit in scon register. software may examine fe bit after each reception to check for data errors. once set, only soft - ware or a chip reset clears fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when the framing error detection feat ure is enabled, ri rises on stop bit instead of the last data bit as detailed in figure 18-17 . figure 18-11. framing error block diagram 18.4.4 baud rate sele ction (modes 1 and 3) in modes 1 and 3, the baud rate is derived either from the timer 1 or the internal baud rate generator and allows different baud rate in reception and transmission. as shown in figure 18-12 , the selection is done using rbck and tbck bits in bdrcon register. figure 18-13 gives the baud rate calculation formulas for each baud rate source. table 90 details internal baud rate gene rator configuration for different peripheral clock frequencies and gives baud rates closer to the standard baud rates. figure 18-12. baud rate source selection (modes 1 and 3) sm0 1 0 smod0 pcon.6 sm0/fe scon.7 framing error controller fe 0 1 rbck bdrcon.2 t1 clock to serial ibrg clock rx port 0 1 tbck bdrcon.3 t1 clock to serial ibrg clock tx port 16 16
113 4173d?usb?02/06 at89c5132 figure 18-13. baud rate formulas (modes 1 and 3) notes: 1. these frequencies are achieved in x1 mode, f per = f osc 2. 2. these frequencies are achieved in x2 mode, f per = f osc . 18.4.5 baud ra te selection (mode 2) in mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 of the periph - eral clock frequency. as shown in figure 18-14 the selection is done using smod1 bit in pcon register. figure 18-15 gives the baud rate calculation formula depending on the selection. table 90. baud rate genera tor configuration baud rate f per = 6 mhz (1) f per = 8 mhz (1) f per = 10 mhz (1) spd smod 1 brl error %spd smod 1brl error % spd smod 1 brl error % 115200 ------------ 57600 ----112473.55112451.36 38400 1 1 246 2.34 1 1 243 0.16 1 1 240 1.73 19200 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 9600 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 4800 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16 baud rate f per = 12 mhz (2) f per = 16 mhz (2) f per = 20 mhz (2) spd smod 1 brl error %spd smod 1brl error % spd smod 1 brl error % 115200 ----112473.55112451.36 57600 1 1 243 0.16 1 1 239 2.12 1 1 234 1.36 38400 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 19200 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 9600 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16 4800 1 1 100 0.16 1 1 48 0.16 1 0 126 0.16 baud_rate= 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f per brl= 256 - 6 (1-spd) ? 32 ? baud_rate 2 smod1 ? f per baud_rate= 6 ? 32 ? (256 -th1) 2 smod1 ? f per th1= 256 - 192 ? baud_rate 2 smod1 ? f per a. ibrg formula b. t1 formula
114 4173d?usb?02/06 at89c5132 figure 18-14. baud rate generator selection (mode 2) figure 18-15. baud rate formula (mode 2) 18.5 multiprocessor communication (modes 2 and 3) modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. to enable this feature, set sm2 bit in scon register. wh en the multiprocessor co mmunication feature is enabled, the serial port can differentiate be tween data frames (ninth bit clear) and address frames (ninth bit set). this allows the at89c5132 to function as a slave processor in an environ - ment where multiple slave processors share a single serial line. when the multiprocessor communication feature is enabled, the receiver ignores frames with the ninth bit clear. the receiver examines frames with the ninth bit set for an address match. if the received address matches the slaves address, the receiver hardware sets rb8 and ri bits in scon register, generating an interrupt. the addressed slave?s software then clears sm2 bit in scon register and prepares to receive the data bytes. the other slaves are unaffected by these data bytes because they are waiting to respond to their own addresses. 18.6 automatic a ddress recognition the automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor commu - nication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, the automatic address recognition feature in mode 1 may be enabled. in this configu - ration, the stop bit takes the place of the nint h data bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. to support automatic address recognition, a devic e is identified by a given address and a broad - cast address. note: the multiprocessor communication and auto matic address recogniti on features cannot be enabled in mode 0 (i.e, setting sm2 bit in scon register in mode 0 has no effect). 18.6.1 given address each device has an individual address that is sp ecified in saddr register; the saden register is a mask byte that contains don?t care bits (defined by zeros) to form the device?s given 0 1 smod1 pcon.7 per clock 2 16 to serial port baud_rate = 32 2 smod1 ? f per
115 4173d?usb?02/06 at89c5132 address. the don?t care bits provide the flexibilit y to address one or more slaves at a time. the following example illustrates ho w a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr = 0101 0110b saden = 1111 1100b given = 0101 01xxb the following is an example of how to use gi ven addresses to addr ess different slaves: slave a: saddr = 1111 0001b saden = 1111 1010b given = 1111 0x0xb slave b: saddr = 1111 0011b saden = 1111 1001b given = 1111 0xx1b slave c: saddr = 1111 0011b saden = 1111 1101b given = 1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don?t-care bit; for slaves b and c, bit 0 is a 1. to communicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 0; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves a and b, but not slave c, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). 18.6.2 broadcast address a broadcast address is formed from the logica l or of the saddr and saden registers with zeros defined as don?t-care bits, e.g.: saddr = 0101 0110b saden = 1111 1100b (saddr | saden)=1111 111xb the use of don?t-care bits provid es flexibility in defining the bro adcast address, however in most applications, a broadcast address is ffh . the following is an example of using broadcast addresses: slave a: saddr = 1111 0001b saden = 1111 1010b given = 1111 1x11b, slave b: saddr = 1111 0011b saden = 1111 1001b given = 1111 1x11b, slave c: saddr = 1111 0010b saden = 1111 1101b given = 1111 1111b, for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send the address ffh . to communicate with slaves a and b, but not slave c, the master must send the address fbh .
116 4173d?usb?02/06 at89c5132 18.6.3 reset address on reset, the saddr and saden registers are init ialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all don?t-care bits). this ensures that the serial port is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition. 18.7 interrupt the serial i/o port handles two interrupt source s that are the ?end of re ception? (ri in scon) and ?end of transmission? (ti in scon) flags. as shown in figure 18-16 these flags are com - bined together to appear as a single interrupt so urce for the c51 core. flags must be cleared by software when executing the serial interrupt service routine. the serial interrupt is enabled by setting es bit in ien0 register. this assumes interrupts are glo - bally enabled by setting ea bit in ien0 register. depending on the selected mode and whether the fram ing error detection is enabled or not, ri flag is set during the stop bit or during the ninth bit as detailed in figure 18-17 . figure 18-16. serial i/o interrupt system figure 18-17. interrupt waveforms 18.8 registers table 91. scon register es ien0.4 serial i/o interrupt request ti scon.1 ri scon.0 rxd d0d1d2d3d4d5d6d7 start bit 8-bit data stop bit ri smod0 = x fe smod0 = 1 a. mode 1 b. mode 2 and 3 rxd d0d1d2d3d4d5d6 d8 start bit 9-bit data stop bit ri smod0 = 1 fe smod0 = 1 d7 ri smod0 = 0
117 4173d?usb?02/06 at89c5132 scon (s:98h) ? serial control register reset value = 0000 0000b table 92. sbuf register sbuf (s:99h) ? serial buffer register reset value = xxxx xxxxb 76543210 fe/sm0 ovr/sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit to select this function, set smod0 bit in pcon register. set by hardware to indicate an invalid stop bit. must be cleared by software. sm0 serial port mode bit 0 refer to table 89 for mode selection. 6sm1 serial port mode bit 1 refer to table 89 for mode selection. 5sm2 serial port mode bit 2 set to enable the multiprocessor communication and automatic address recognition features. clear to disable the multiprocessor comm unication and automatic address recognition features. 4ren receiver enable bit set to enable reception. clear to disable reception. 3tb8 transmit bit 8 modes 0 and 1: not used. modes 2 and 3: software writes the ninth data bit to be transmitted to tb8. 2rb8 receiver bit 8 mode 0: not used. mode 1 (sm2 cleared): set or cleared by hardware to reflect the stop bit received. modes 2 and 3 (sm2 set): set or cleared by hardware to reflect the ninth bit received. 1ti transmit interrupt flag set by the transmitter after the last data bit is transmitted. must be cleared by software. 0ri receive interrupt flag set by the receiver after the st op bit of a frame has been received. must be cleared by software. 76543210 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 bit number bit mnemonic description 7 - 0 sd7:0 serial data byte read the last data received by the serial i/o port. write the data to be transmitted by the serial i/o port.
118 4173d?usb?02/06 at89c5132 table 93. saddr register saddr (s:a9h) ? slave individual address register reset value = 0000 0000b table 94. saden register saden (s:b9h) ? slave individ ual address mask byte register reset value = 0000 0000b table 95. bdrcon register bdrcon (s:92h) ? baud rate generator control register 76543210 sad7 sad6 sad5 sad4 sad3 sad2 sad1 sad0 bit number bit mnemonic description 7 - 0 sad7:0 slave individual address. 76543210 sae7 sae6 sae5 sae4 sae3 sae2 sae1 sae0 bit number bit mnemonic description 7 - 0 sae7:0 slave address mask byte. 76543210 - - - brr tbck rbck spd m0src bit number bit mnemonic description 7-5 - reserved the value read from these bits is i ndeterminate. do not set these bits. 4brr baud rate run bit set to enable the baud rate generator. clear to disable the baud rate generator. 3tbck transmission baud rate selection bit set to select the baud rate generator as transmission baud rate generator. clear to select the timer 1 as transmission baud rate generator. 2rbck reception baud rate selection bit set to select the baud rate generator as reception baud rate generator. clear to select the timer 1 as reception baud rate generator. 1 spd baud rate speed bit set to select high speed baud rate generation. clear to select low speed baud rate generation. 0m0src mode 0 baud rate source bit set to select the variable baud rate generator in mode 0. clear to select fixed baud rate in mode 0.
119 4173d?usb?02/06 at89c5132 reset value = xxx0 0000b table 96. brl register brl (s:91h) ? baud rate generator reload register reset value = 0000 0000b 76543210 brl7 brl6 brl5 brl4 brl3 brl2 brl1 brl0 bit number bit mnemonic description 7-0 brl7:0 baud rate reload value.
120 4173d?usb?02/06 at89c5132 19. synchronous peripheral interface the at89c5132 implement a synchronous periphera l interface with master and slave modes capability. figure 19-1 shows an spi bus configuration using the at89c5132 as master connected to slave peripherals. figure 19-2 shows an spi bus configuration us ing the at89c5132 as slave of an other master. the bus is made of three wires co nnecting all the devices together: ? master output slave input (mosi): it is used to transfer data in series from the master to a slave. it is driven by the master. ? master input slave output (miso): it is used to transfer data in series from a slave to the master. it is driven by the selected slave. ? serial clock (sck): it is used to synchronize the data transmission both in and out of the devices through their mosi and miso lines. it is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. each slave peripheral is selected by one slave select pin ( ss ). if there is only one slave, it may be continuously selected with ss tied to a low level. otherwise, the at89c5132 may select each device by software through port pins (pn.x). special care should be taken not to select two slaves at the same time to avoid bus conflicts. figure 19-1. typical master spi bus configuration figure 19-2. typical slave spi bus configuration at89c5132 dataflash 1 ss miso mosi sck p4.0 p4.1 p4.2 pn.z pn.y pn.x so si sck dataflash 2 ss so si sck lcd controller ss so si sck master slave 1 ss miso mosi sck ssn ss1 ss0 so si sck slave 2 ss so si sck at89c5132 slave n ss miso mosi sck
121 4173d?usb?02/06 at89c5132 19.1 description the spi controller interfaces with the c51 core th rough three special function registers: spcon, the spi control register (see table 98 ); spsta, the spi st atus register (see table 99 ); and spdat, the spi data register (see table 100 ). 19.1.1 master mode the spi operates in master mode when the mstr bit in spcon is set. figure 19-3 shows the spi block diagram in master mode. only a master spi module can initiate transmissions. software begins th e transmission by writing to spdat. writing to spdat writes to the shift register while reading spdat reads an intermediate register updated at the end of each transfer. the byte begins shifting out on the mosi pin under the control of the bit rate generator. this generator also controls the shift register of the slave peripheral through the sck output pin. as the byte shifts out, another byte shifts in from the slave peripheral on the miso pin. the byte is transmitted most significant bit (msb) first. the end of transfer is signalled by spif being set. in case of the at89c5132 is the only master on the bus, it can be useful not to use ss pin and get it back to i/o functionality. this is achieved by setting ssdis bit in spcon. figure 19-3. spi master mode block diagram note: mstr bit in spcon is se t to select master mode. 19.1.2 slave mode the spi operates in slave mode when the mstr bit in spcon is cleared and data has been loaded in spdat. figure 19-4 shows the spi block diagram in slave mode. in slave mode, before data transmis - sion occurs, the ss pin of the slave spi must be asserted to low level. ss must remain low until the transmission of the byte is complete. in the slave spi module, data enters the shift register through the mosi pin under the control of the seri al clock provided by the master spi module on the sck input pin. when the master starts a transmission, the data in the shift register begins shifting out on the miso pin. the end of transfer is signaled by spif being set. bit rate generator spr2:0 spcon mosi/p4.1 miso/p4.0 sck/p4.2 cpol spcon.3 spen spcon.6 cpha spcon.2 per clock 8-bit shift register spdat wr iq internal bus spdat rd control and clock logic modf spsta.4 ss /p4.3 ssdis spcon.5 wcol spsta.6 spif spsta.7
122 4173d?usb?02/06 at89c5132 in case of the at89c5132 is the only slave on th e bus, it can be useful not to use ss pin and get it back to i/o functionality. this is achieved by setting ssdis bit in spcon. this bit has no effect when cpha is cleared (see section "ss management", page 123 ). figure 19-4. spi slave mode block diagram note: mstr bit in spcon is cleared to select slave mode. 19.1.3 bit rate the bit rate can be selected from seven predef ined bit rates using the spr2, spr1 and spr0 control bits in spcon according to table 97 . these bit rates are derived from the peripheral clock (f per ) issued from the clock controller block as detailed in section ?clock controller?, page 12 . table 97. serial bit rates notes: 1. these frequencies are achieved in x1 mode, f per = f osc 2. 2. these frequencies are achieved in x2 mode, f per = f osc . 19.1.4 data transfer the clock polarity bit (cpol in spcon) defi nes the default sck line level in idle state (1) while the clock phase bit (cpha in spcon) defines the edges on wh ich the input data are sampled and the edges on which the output data are shifted (see figure 19-5 and figure 19-6 ). the si signal is output from the selected slave and the so signal is the output from the master. the miso/p4.2 mosi/p4.1 ss /p4.3 spif spsta.7 cpol spcon.3 cpha spcon.2 8-bit shift register spdat wr iq internal bus spdat rd sck/p4.2 ssdis spcon.5 control and clock logic spr2 spr1 spr0 bit rate (khz) vs f per f per divider 6 mhz (1) 8 mhz (1) 10 mhz (1) 12 mhz (2) 16 mhz (2) 20 mhz (2) 0 0 0 3000 4000 5000 6000 8000 10000 2 0 0 1 1500 2000 2500 3000 4000 5000 4 0 1 0 750 1000 1250 1500 2000 2500 8 0 1 1 375 500 625 750 1000 1250 16 1 0 0 187.5 250 312.5 375 500 625 32 1 0 1 93.75 125 156.25 187.5 250 312.5 64 1 1 0 46.875 62.5 78.125 93.75 125 156.25 128 1 1 1 6000 8000 10000 12000 16000 20000 1
123 4173d?usb?02/06 at89c5132 at89c5132 captures data from the si line while the selected slave captures data from the so line. for simplicity, the following figures depict the spi waveforms in idealized form and do not pro - vide precise timing information. for timing parameters refer to the section ?ac characteristics?. note: 1. when the peripher al is disabled (spen = 0), default sck line is high level. figure 19-5. data transmission format (cpha = 0) figure 19-6. data transmission format (cpha = 1) 19.1.5 ss management figure 19-5 shows an spi transmission with cpha = 0, where the first sck edge is the msb capture point. therefore the slave starts to output its msb as soon as it is selected: ss asserted to low level. ss must then be deasserted between each byte transmission (see figure 19-7 ). spdat must be loaded with data before ss is asserted again. 1 2 3 4 5 6 7 8 msb bit 1 lsb bit 2 bit 4 bit 3 bit 6 bit 5 bit 1 bit 2 bit 4 bit 3 bit 6 bit 5 msb lsb mosi (from master) miso (from slave) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number ss (to slave) to capture point 1 2 3 4 5 6 7 8 msb bit 1 lsb bit 2 bit 4 bit 3 bit 6 bit 5 bit 1 bit 2 bit 4 bit 3 bit 6 bit 5 msb lsb mosi (from master) miso (from slave) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number ss (to slave) capture point
124 4173d?usb?02/06 at89c5132 figure 19-6 shows an spi transmission with cpha = 1, wh ere the first sck edge is used by the slave as a start of transmission signal. therefore ss may remain asserted between each byte transmission (see figure 19-7 ). figure 19-7. ss timing diagram 19.1.6 error conditions the following flags signal the spi error conditions: ? modf in spsta signals a mode fault. modf flag is relevant only in master mode when ss usage is enabled (ssdis bit cleared). it signals when set that another master on the bus has asserted ss pin and so, may create a conflict on the bus with two masters sending data at the same time. a mode fault automatically disables the spi ( spen cleared) and config ures the spi in slave mode (mstr cleared). modf flag can trigger an interrupt as explained in section "interrupt", page 124 . modf flag is cleared by reading spsta and re-c onfiguring spi by writing to spcon. ? wcol in spsta signals a write collision. wcol flag is set when spdat is loaded while a tr ansfer is on-going. in this case, data is not written to spdat and transfer continues unin terrupted. wcol flag does not trigger any interrupt and is relevant jointly with spif flag. wcol flag is cleared after re ading spsta and writi ng new data to spdat while no transfer is ongoing. 19.2 interrupt the spi handles two interrupt sources; the ?e nd of transfer? and the ?mode fault? flags. as shown in figure 19-8 these flags are comb ined together to appear as a single interrupt source for the c51 core. the spif flag is set at th e end of an 8-bit shift in and out and is cleared by reading spsta and then reading from or writing to spdat. the modf flag is set in case of mode fault error and is clea red by reading spsta and then writ - ing to spcon. the spi interrupt is enabled by setting espi bit in ien1 register. this assumes interrupts are globally enabled by setting ea bit in ien0 register. figure 19-8. spi interrupt system 19.3 configuration the spi configuration is made through spcon. ss (cpha = 1) ss (cpha = 0) si/so byte 1 byte 2 byte 3 espi ien1.2 spi controller interrupt request spif spsta.7 modf spsta.4
125 4173d?usb?02/06 at89c5132 19.3.1 master configuration the spi operates in master mode when the mstr bit in spcon is set. 19.3.2 slave configuration the spi operates in slave mode when the mstr bit in spcon is cleared and data has been loaded in spdat. 19.3.3 data exchange there are two possible policies to exchange data in master and slave modes: ? polling ? interrupts 19.3.4 master mode with polling policy figure 19-9 shows the initialization phas e and the transfer phase flow s using the polling policy. using this flow prevents any overrun error occurrence. ? the bit rate is se lected according to table 97 . ? the transfer format depends on the slave peripheral. ? ss may be deasserted between transfers depending also on the slave peripheral. ? spif flag is cleared when reading spdat (spsta has been read before by the ?end of transfer? check). this policy provides the fastest effective transm ission and is well adapted when communicating at high speed with other microcontrollers. however, the procedure may then be interrupted at any time by higher priority tasks.
126 4173d?usb?02/06 at89c5132 figure 19-9. master spi polling policy flows 19.3.5 master mode wi th interrupt policy figure 19-10 shows the initialization phase and the tran sfer phase flows using the interrupt pol - icy. using this flow prevents any overrun error occurrence. ? the bit rate is se lected according to table 97 . ? the transfer format depends on the slave peripheral. ? ss may be deasserted between transfers depending also on the slave peripheral. reading spsta at the beginning of the isr is mandatory for clearing the spif flag. clear is effective when reading spdat. spi initialization polling policy disable interrupt spie = 0 spi transfer polling policy end of transfer? spif = 1? select master mode mstr = 1 select bit rate program spr2:0 select format program cpol & cpha enable spi spen = 1 select slave pn.x = l start transfer write data in spdat last transfer? get data received read spdat deselect slave pn.x = h
127 4173d?usb?02/06 at89c5132 figure 19-10. master spi interrupt policy flows 19.3.6 slave mode with polling policy figure 19-11 shows the initialization phase and the tr ansfer phase flows using the polling policy. the transfer format depends on the master controller. spif flag is cleared when reading spdat (spsta has been read before by the ?end of recep - tion? check). this policy provides the fastest effective transm ission and is well adapted when communicating at high speed with other microcontrollers. howe ver, the procedure may be interrupted at any time by higher priority tasks. spi initialization interrupt policy enable interrupt espi =1 spi interrupt service routine select master mode mstr = 1 select bit rate program spr2:0 select format program cpol & cpha enable spi spen = 1 read status read spsta start new transfer write data in spdat last transfer? get data received read spdat disable interrupt spie = 0 select slave pn.x = l start transfer write data in spdat deselect slave pn.x = h
128 4173d?usb?02/06 at89c5132 figure 19-11. slave spi polling policy flows 19.3.7 slave mode wi th interrupt policy figure 19-10 shows the initialization phase and the tr ansfer phase flows using the interrupt policy. the transfer format depends on the master controller. reading spsta at the beginning of the isr is mandatory for clearing the spif flag. clear is effective when reading spdat. spi initialization polling policy disable interrupt spie = 0 spi transfer polling policy data received? spif = 1? select slave mode mstr = 0 select format program cpol & cpha enable spi spen = 1 prepare next transfer write data in spdat get data received read spdat prepare transfer write data in spdat
129 4173d?usb?02/06 at89c5132 figure 19-12. slave spi interrupt policy flows 19.4 registers table 98. spcon register spcon (s:c3h) ? spi control register spi initialization interrupt policy enable interrupt espi =1 spi interrupt service routine select slave mode mstr = 0 select format program cpol & cpha enable spi spen = 1 get status read spsta prepare new transfer write data in spdat get data received read spdat prepare transfer write data in spdat 76543210 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic description 7 spr2 spi rate bit 2 refer to table 97 for bit rate description. 6 spen spi enable bit set to enable the spi interface. clear to disable the spi interface. 5 ssdis slave select input disable bit set to disable ss in both master and slave modes. in slave mode this bit has no effect if cpha = 0. clear to enable ss in both master and slave modes. 4mstr master mode select set to select the master mode. clear to select the slave mode. 3cpol spi clock polarity bit (1) set to have the clock output set to high level in idle state. clear to have the clock output set to low level in idle state. 2cpha spi clock phase bit set to have the data sampled when the clock returns to idle state (see cpol). clear to have the data sampled when the clock leaves the idle state (see cpol).
130 4173d?usb?02/06 at89c5132 reset value = 0001 0100b note: 1. when the spi is disabled, sck outputs high level. table 99. spsta register spsta (s:c4h) ? spi status register reset value = 00000 0000b table 100. spdat register spdat (s:c5h) ? synchronous serial data register reset value = xxxx xxxxb 1 - 0 spr1:0 spi rate bits 0 and 1 refer to table 97 for bit rate description. 76543210 spif wcol - modf - - - - bit number bit mnemonic description 7 spif spi interrupt flag set by hardware when an 8-bit shift is completed. cleared by hardware when reading or writing spdat after reading spsta. 6wcol write collision flag set by hardware to indicate that a collision has been detected. cleared by hardware to indicate t hat no collision has been detected. 5- reserved the values read from this bit is indeterminate. do not set this bit. 4modf mode fault set by hardware to indicate that the ss pin is at an appropriate level. cleared by hardware to indicate that the ss pin is at an inappropriate level. 3:0 - reserved the values read from these bits are i ndeterminate. do not set these bits. 76543210 spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 bit number bit mnemonic description 7 - 0 spd7:0 synchronous serial data bit number bit mnemonic description
131 4173d?usb?02/06 at89c5132 20. two-wire interface (twi) controller the at89c5132 implements a twi controller s upporting the four standard master and slave modes with multimaster ca pability. thus, it allows connecti on of slave devices like lcd control - ler, audio dac, etc., but also external master control ling where the at89c5132 is used as a peripheral of a host. the twi bus is a bi-directional twi serial commu nication standard. it is designed primarily for simple but efficient integrated circuit control. the system is comprised of 2 lines, scl (serial clock) and sda (serial data) that carry information between the ics connected to them. the serial data transfer is limited to 100 kbit/s in low speed mode, however, some higher bit rates can be achieved depending on the oscillator frequency. various communication configurations can be designed using this bus. figure 20-1 shows a typical twi bus configuration using the at89c5132 in master and slave modes. all the de vices connected to the bus can be master and slave. figure 20-1. typical twi bus configuration 20.1 description the cpu interfaces to the twi logic via the follo wing four 8-bit special function registers: the synchronous serial control register (sscon sfr, see table 26 ), the synchronous serial data register (ssd at sfr, see table 28 ), the synchronous serial status register (sssta sfr, see table 27 ) and the synchr onous serial address r egister (ssadr sfr, see table 29 ). sscon is used to enable the contro ller, to program the bit rate (see table 26 ), to enable slave modes, to acknowledge or not a received data , to send a start or a stop condition on the twi bus, and to acknowledge a serial interrupt. a hardware reset disables the twi controller. sssta contains a status code which reflects t he status of the twi logic and the twi bus. the three least significant bits are always zero. the five most significant bits contains the status code. there are 26 possible status codes. when sssta contains f8h, no relevant state infor - mation is available and no serial interrupt is requested. a valid status code is available in sssta after ssi is set by hardware and is still pr esent until ssi has been reset by software. table 20 to table 20-6 give the status for both master an d slave modes and miscellaneous states. ssdat contains a byte of serial data to be tran smitted or a byte which has just been received. it is addressable while it is not in process of shi fting a byte. this occurs when twi logic is in a defined state and the serial interrupt flag is set. data in ssdat remains stable as long as ssi is set. while data is bein g shifted out, data on the bus is si multaneously shifted in; ssdat always contains the last byte present on the bus. ssadr may be loaded with the 7 - bit slave address (7 most significant bits) to which the con - troller will respond when programmed as a slave transmitter or receiver. the lsb is used to enable general call address (00h) recognition. figure 20-2 shows how a data transfer is accomplished on the twi bus. at89c5132 master/slave lcd display audio dac p1.6/scl p1.7/sda rp rp host microprocessor scl sda
132 4173d?usb?02/06 at89c5132 figure 20-2. complete data tr ansfer on twi bus the four operating modes are: ? master transmitter ? master receiver ? slave transmitter ? slave receiver data transfer in each mode of operation are shown in figure 20-3 through figure 20-6 . these figures contain the following abbreviations: a acknowledge bit (low level at sda) a not acknowledge bit (high level on sda) data 8-bit data byte s start condition p stop condition mr master receive mt master transmit sla slave address gca general call address (00h) r read bit (high level at sda) w write bit (low level at sda) in figure 20-3 through figure 20-6 , circles are used to indicate when the serial interrupt flag is set. the numbers in the circles sh ow the status code held in ss sta. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial tr ansfer is suspended until the serial interrupt flag is cleared by software. when the serial interrupt routine is entered, the status code in sssta is used to branch to the appropriate service routine. for each status code, the required so ftware action and details of the following serial transfer are given in table 20 through table 20-6 . 20.1.1 bit rate the bit rate can be selected from seven predefined bit rates or from a programmable bit rate generator using the sscr2, sscr1, and sscr0 control bits in sscon (see table 26 ). the predefined bit rates are derived from the peripheral clock (f per ) issued from the clock controller block as detailed in section "oscillator", page 12 , while bit rate generator is based on timer 1 overflow output. s slave address scl sda msb r/w direction ack signal nth data byte ack signal p/s bit from receiver from receiver 12 89 12 89 clock line held low while serial interrupts are serviced
133 4173d?usb?02/06 at89c5132 note: 1. these bit rates are outside of the low speed standard specification limited to 100 khz but can be used with high speed twi components limited to 400 khz. 20.1.2 master transmitter mode in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see figure 20-3 ). before the master transmi tter mode can be entered, ssc on must be initialized as follows: sscr2:0 define the serial bit rate (see table 19 ). sspe must be set to enable the controller. sssta, sssto and ssi must be cleared. the master transmitter mode may now be entered by setting the sssta bit. the twi logic will now monitor the twi bus and generate a start co ndition as soon as t he bus becomes free. when a start condition is transmitted, the serial interrupt flag (ssi bit in sscon) is set, and the status code in sssta is 08h. this status must be used to vector to an interrupt routine that loads ssdat with the slave address and the data direction bit (sla+w). the serial interrupt flag (ssi) must then be cleared before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, ssi is set ag ain and a number of status code in sssta are possible. there are 18h, 20h or 38h for the master mode and also 68h, 78h or b0h if the slave mode was enabled (ssaa = logic 1). the appropriate action to be taken for each of these status code is detailed in table 20 . this scheme is repe ated until a stop condition is transmitted. sspe and sscr2:0 are not affected by the seri al transfer and are not referred to in table 20 . after a repeated start condition (state 10h) the controller may switch to the master receiver mode by loading ssdat with sla+r. 20.1.3 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 20-4 ). the transfer is initialized as in the master transmitter mode. when the start con - dition has been transmitted, the interrupt routine must load ssdat with the 7 - bit slave address and the data direction bit (sla+r). the serial interrupt flag (ssi) must then be cleared before the serial transfer can continue. table 19. serial clock rates sscrx bit frequency (khz) f per divided by 210 f per = 6 mhz f per = 8 mhz f per = 10 mhz 0 0 0 47 62.5 78.125 128 0 0 1 53.5 71.5 89.3 112 0 1 0 62.5 83 104.2 (1) 96 0 1 1 75 100 125 (1) 80 1 0 0 12.5 16.5 20.83 480 1 0 1 100 133.3 (1) 166.7 (1) 60 1 1 0 200 (1) 266.7 (1) 333.3 (1) 30 1 1 1 0.5 < ? < 125 (1) 0.67 < ? < 166.7 (1) 0.81 < ? < 208.3 (1) 96 ? (256 ? reload value timer 1) sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 bit rate 1 0 0 0 x bit rate bit rate
134 4173d?usb?02/06 at89c5132 when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag is set again and a number of status code in sssta are possible. there are 40h, 48h or 38h for the master mode and also 68h, 78h or b0h if the slave mode was enabled (ssaa = logic 1). the appro priate action to be taken for each of these status code is detailed in table 20-6 . this scheme is repeated until a stop condition is transmitted. sspe and sscr2:0 are not affected by the seri al transfer and are not referred to in table 20-6 . after a repeated start condition (state 10h) the controller may switch to the master transmitter mode by loading ssdat with sla+w. 20.1.4 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 20-5 ). to initiate the slave receiver mo de, ssadr and sscon must be loaded as follows: the upper 7 bits are the addre sses to which the controller will respond when addressed by a master. if the lsb (ssgc) is se t, the controller will respond to t he general call address (00h); otherwise, it ignores the general call address. sscr2:0 have no effect in the slave mode. sspe must be set to enable the controller. the ssaa bit must be set to enable the own slave address or the general call address acknowledg - ment. sssta, sssto and ssi must be cleared. when ssadr and sscon have been initia lized, the controlle r waits until it is addressed by its own slave address followed by the data direction bit which must be logic 0 (w) for operating in the slave receiver mode. after its own slave addr ess and the w bit has been received, the serial interrupt flag is set and a valid st atus code can be read from sssta. this stat us code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status code is detailed in table 20-6 and table 24 . the slave receiver mode may also be entered if arbitration is lost while the controller is in the ma ster mode (see states 68h and 78h). if the ssaa bit is reset during a transfer, the controller will return a not acknowledg e (logic 1) to sda after the next received data by te. while ssaa is reset, the controller does not respond to its own slave address. however, the twi bus is still monitored and address rec ognition may be resumed at any time by setti ng ssaa. this means that the ssaa bi t may be used to temporarily isolate the controller from the twi bus. 20.1.5 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 20-6 ). data transfer is init ialized as in the slave receiver mode. when ssadr and sscon have been initialized, the controller waits un til it is addressed by its own slave address followed by the data direction bit which must be lo gic 1 (r) for operating in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag is set and a valid status code can be read from ssst a. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status code is detailed in table 24 . the slave transmitter mode may also be entered if arbitration is lost while the controller is in the master mode (see state b0h). ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 ssgc ?????????? own slave address ?????????? x sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 x10001xx
135 4173d?usb?02/06 at89c5132 if the ssaa bit is reset during a transfer, the controller will transmit the last byte of the transfer and enter state c0h or c 8h. the controller is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the master receiver receives all 1?s as serial data. while ssaa is reset, the contro ller does not respond to its own slave address. however, the twi bus is still m onitored and address recognition may be resumed at any time by setting ssaa. this means that the ssaa bit may be used to temporarily isolate the controller from the twi bus. 20.1.6 miscellaneous states there are 2 sssta codes that do not correspond to a defined twi hardware state (see table 25 ). these are discussed below. status f8h indicates that no relevant information is available because the serial interrupt flag is not yet set. this occurs between other states and when the controller is not involved in a serial transfer. status 00h indicates that a bus error has occurred during a serial transfer. a bus error is caused when a start or a stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial tr ansfer of an address by te, a data byte, or an acknowledge bit. when a bus error occurs, ssi is set. to recover from a bus error, the sssto flag must be set and ssi must be cleared. this causes the controller to enter the not addressed slave mode and to clear the sssto flag (no ot her bits in s1con are affected). the sda and scl lines are released and no stop condition is transmitted. note: the twi controller interfaces to the external twi bus via 2 port 1 pins: p1.6/scl (serial clock line) and p1.7/sda (serial data line). to avoid low level asserting and conflict on these lines when the twi controller is enabled, the output latches of p1.6 and p1.7 must be set to logic 1.
136 4173d?usb?02/06 at89c5132 figure 20-3. format and states in the master transmitter mode data 20h a sla 08h mt mr successful transmis- sion to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave not acknowledge received data a from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contain ed in sssta) corresponds to a defined state of the twi bus sw 18h a p 28h sla sw r a p 10h 30h a p 38h a or a continues other master 38h a or a continues other master 68h a continues other master 78h b0h nnh after a data byte to corresponding states in slave mode
137 4173d?usb?02/06 at89c5132 figure 20-4. format and states in the master receiver mode a data 48h a sla 08h mr mt successful reception from a slave transmitter next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sssta) corresponds to a defined state of the twi bus sr 40h a p 58h sla sr w a p 10h 38h a continues other master 38h a or a continues other master 68h a continues other master 78h b0h nnh to corresponding states in slave mode data 50h
138 4173d?usb?02/06 at89c5132 figure 20-5. format and states in the slave receiver mode a data 68h a sla reception of the own slave address and one or more last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes arbitration lost as master and addressed as slave by general call data a from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sssta) corresponds to a defined state of the twi bus sw 60h a p or s 80h a nnh data 80h a0h 88h a p or s a data 78h a general call 70h a p or s 90h a data 90h a0h 98h a p or s data bytes. all are acknowledged last data byte received is not acknowledged
139 4173d?usb?02/06 at89c5132 figure 20-6. format and states in the slave transmitter mode a data b0h a sla data a from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sssta) corresponds to a defined state of the twi bus sr a8h a p or s c0h all 1?s ap or s c8h nnh data b8h a arbitration lost as master and addressed as slave reception of the own slave address and transmission of one or more data bytes. last data byte transmitted. switched to not addressed slave (ssaa = 0).
140 4173d?usb?02/06 at89c5132 table 20. status for master transmitter mode status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa 08h a start condition has been transmitted write sla+w x 0 0 x sla+w will be transmitted. 10h a repeated start condition has been transmitted write sla+w write sla+r x x 0 0 0 0 x x sla+w will be transmitted. sla+r will be transmitted. logic will switch to master receiver mode 18h sla+w has been transmitted; ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 20h sla+w has been transmitted; not ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 28h data byte has been transmitted; ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 30h data byte has been transmitted; not ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 38h arbitration lost in sla+w or data bytes no ssdat action no ssdat action 0 1 0 0 0 0 x x twi bus will be released and not addressed slave mode will be entered. a start condition will be transmitted when the bus becomes free.
141 4173d?usb?02/06 at89c5132 table 21. status for master receiver mode status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa 08h a start condition has been transmitted write sla+r x 0 0 x sla+r will be transmitted. 10h a repeated start condition has been transmitted write sla+r write sla+w x x 0 0 0 0 x x sla+r will be transmitted. sla+w will be transmitted. logic will switch to master transmitter mode. 38h arbitration lost in sla+r or not ack bit no ssdat action no ssdat action 0 1 0 0 0 0 x x twi bus will be released and not addressed slave mode will be entered. a start condition will be transmitted when the bus becomes free. 40h sla+r has been transmitted; ack has been received no ssdat action no ssdat action 0 0 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 48h sla+r has been transmitted; not ack has been received no ssdat action no ssdat action no ssdat action 1 0 1 0 1 1 0 0 0 x x x repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 50h data byte has been received; ack has been returned read data byte read data byte 0 0 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 58h data byte has been received; not ack has been returned read data byte read data byte read data byte 1 0 1 0 1 1 0 0 0 x x x repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset.
142 4173d?usb?02/06 at89c5132 table 22. status for slave receiver mode with own slave address status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa 60h own sla+w has been received; ack has been returned no ssdat action no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 68h arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no ssdat action no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 80h previously addressed with own sla+w; data has been received; ack has been returned read data byte read data byte x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 88h previously addressed with own sla+w; data has been received; not ack has been returned read data byte read data byte read data byte read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free. a0h a stop condition or repeated start condition has been received while still addressed as slave no ssdat action no ssdat action no ssdat action no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free.
143 4173d?usb?02/06 at89c5132 table 23. status for slave receiver mode with general call address status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa 70h general call address has been received; ack has been returned no ssdat action no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 78h arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no ssdat action no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 90h previously addressed with general call; data has been received; ack has been returned read data byte read data byte x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 98h previously addressed with general call; data has been received; not ack has been returned read data byte read data byte read data byte read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free. a0h a stop condition or repeated start condition has been received while still addressed as slave no ssdat action no ssdat action no ssdat action no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free.
144 4173d?usb?02/06 at89c5132 table 24. status for slave transmitter mode status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa a8h own sla+r has been received; ack has been returned write data byte write data byte x x 0 0 0 0 0 1 last data byte will be transmitted. data byte will be transmitted. b0h arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned write data byte write data byte x x 0 0 0 0 0 1 last data byte will be transmitted. data byte will be transmitted. b8h data byte in ssdat has been transmitted; ack has been received write data byte write data byte x x 0 0 0 0 0 1 last data byte will be transmitted. data byte will be transmitted. c0h data byte in ssdat has been transmitted; not ack has been received no ssdat action no ssdat action no ssdat action no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free. c8h last data byte in ssdat has been transmitted (ssaa= 0); ack has been received no ssdat action no ssdat action no ssdat action no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gc a will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free. table 25. status for miscellaneous states status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa f8h no relevant state information available; ssi = 0 no ssdat action no sscon action wait or proceed current transfer. 00h bus error due to an illegal start or stop condition no ssdat action 0 1 0 x only the internal hardware is affected, no stop condition is sent on the bus. in all cases, the bus is released and sssto is reset.
145 4173d?usb?02/06 at89c5132 20.2 registers table 26. sscon register sscon (s:93h) ? synchronous serial control register reset value = 0000 0000b table 27. sssta register sssta (s:94h) ? synchronous serial status register 76543210 sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 bit number bit mnemonic description 7 sscr2 synchronous serial control rate bit 2 refer to table 19 for rate description. 6 sspe synchronous serial peripheral enable bit set to enable the controller. clear to disable the controller. 5 sssta synchronous serial start flag set to send a start condition on the bus. clear not to send a start condition on the bus. 4 sssto synchronous serial stop flag set to send a stop condition on the bus. clear not to send a stop condition on the bus. 3ssi synchronous serial interrupt flag set by hardware when a serial interrupt is requested. must be cleared by software to acknowledge interrupt. 2 ssaa synchronous serial assert acknowledge flag set to enable slave modes. slave modes are entered when sla or gca (if ssgc set) is recognized. clear to disable slave modes. master receiver mode in progress clear to force a not acknowledge (high level on sda). set to force an acknowledge (low level on sda). master transmitter mode in progress this bit has no specific effect when in master transmitter mode. slave receiver mode in progress clear to force a not acknowledge (high level on sda). set to force an acknowledge (low level on sda). slave transmitter mode in progress clear to isolate slave from the bu s after last data byte transmission. set to enable slave mode. 1 sscr1 synchronous serial control rate bit 1 refer to table 19 for rate description. 0 sscr0 synchronous serial control rate bit 0 refer to table 19 for rate description. 76543210 ssc4 ssc3 ssc2 ssc1 ssc0 0 0 0
146 4173d?usb?02/06 at89c5132 reset value = f8h table 28. ssdat register ssdat (s:95h) ? synchronous serial data register reset value = 1111 1111b table 29. ssadr register ssadr (s:96h) ? synchronous serial address register reset value = 1111 1110b bit number bit mnemonic description 7:3 ssc4:0 synchronous serial status code bits 0 to 4 refer to table 20 to table 20-6 for status description. 2:0 0 always 0. 76543210 ssd7 ssd6 ssd5 ssd4 ssd3 ssd2 ssd1 ssd0 bit number bit mnemonic description 7:1 ssd7:1 synchronous serial address bits 7 to 1 or synchronous serial data bits 7 to 1 0 ssd0 synchronous serial address bit 0 (r/w) or synchronous serial data bit 0 76543210 ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssgc bit number bit mnemonic description 7:1 ssa7:1 synchronous serial slave address bits 7 to 1 0 ssgc synchronous serial general call bit set to enable the general call address recognition. clear to disable the general call address recognition.
147 4173d?usb?02/06 at89c5132 21. analog to digital converter the at89c5132 implement a 2-channel 10-bit (8 true bits) analog to digital converter (adc). first channel of this adc can be used for battery monitoring while the second one can be used for voice sampling at 8 khz. 21.1 description the a/d converter interfaces with the c51 core th rough four special function registers: adcon, the adc control register (see table 31 ); addh and addl, the adc data registers (see table 33 and table 34 ); and adclk, the adc clock register (see table 32 ). as shown in figure 21-1 , the adc is composed of a 10-bit cascaded potentiometric digital to analog converter, connected to the negative input of a comparator. the output voltage of this dac is compared to the analog voltage stored in the sample and hold and coming from ain0 or ain1 input depending on the channel selected (see table 30 ). the 10-bit addat converted value (see formula in figure 21-1 ) is delivered in addh and addl registers, addh is giving the 8 most significant bits while addl is giving the 2 least significant bits. addat figure 21-1. adc structure figure 21-2 shows the timing diagram of a complete co nversion. for simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. for adc charac - teristics and timing parameters refer to the section ?ac characteristics?. 0 1 ain1 ain0 adcs adcon.0 avss sample and hold addh arefp r/2r dac adc clock arefn 8 10 aden adcon.5 adsst adcon.3 adeoc adcon.4 adc interrupt request eadc ien1.3 control + - addl 2 sar addat 1023 v ? in v ref --------------------------- =
148 4173d?usb?02/06 at89c5132 figure 21-2. timing diagram 21.1.1 clock generator the adc clock is generated by division of the peripheral clock (see details in section ?x2 fea - ture?, page 12 ). the division factor is then giv en by adcp4:0 bits in adclk register. figure 21- 3 shows the adc clock generator and its calculation formula (1) . figure 21-3. adc clock generator and symbol caution: note: 1. in all cases, the adc clock frequency may be higher than the maximum f adclk parameter reported in the section ?analog to digital converter?, page 201 . 2. the adcd value of 0 is equivalent to an adcd value of 32. 21.1.2 channel selection the channel on which conversion is performed is se lected by the adcs bit in adcon register according to table 30 . table 30. adc channel selection 21.1.3 conversion precision the 10-bit precision conversion is achieved by st opping the cpu core activity during conversion for limiting the digital noise induced by the core. this mode called the pseudo-idle mode (1),(2) is enabled by setting the adidl bit in adcon register (3) . thus, when conversion is launched (see section "conversion launching", page 149 ), the cpu core is stopped until the end of the con - aden adsst adeoc t setup t conv clk t adclk adcd4:0 adclk adc clock adcclk perclk 2 adcd ? ------------------------- = adc clock symbol adc clock per clock 2 adcs channel 0ain1 1ain0
149 4173d?usb?02/06 at89c5132 version (see section "end of conversion", page 149 ). this bit is cleared by hardware at the end of the conversion. notes: 1. only the cpu activity is frozen, periphe rals are not affected by the pseudo-idle mode. 2. if some interrupts occur during the pseudo-id le mode, they will be delayed and processed, according to their priority after the end of the conversion. 3. concurrently with adsst bit. 21.1.4 configuration the adc configuration consists in progra mming the adc clock as detailed in the section "clock generator", page 148 . the adc is enabled using the aden bit in adcon register. as shown in figure 93, user must wait the setup time (t setup ) before launching any conversion. figure 21-4. adc configuration flow 21.1.5 conversion launching the conversion is launched by setting the adsst bit in adcon register, this bit remains set during the conversion. as soon as the conversion is started, it takes 11 clock periods (t conv ) before the data is available in addh and addl registers. figure 21-5. adc conversion launching flow 21.1.6 end of conversion the end of conversion is signalled by the adeoc flag in adcon register becoming set or by the adsst bit in adcon register becoming cleared. adeoc flag can generate an interrupt if adc configuration enable adc adidl = x aden = 1 wait setup time program adc clock adcd4:0 = xxxxxb adc conversion start select channel adcs = 0-1 start conversion adsst = 1
150 4173d?usb?02/06 at89c5132 enabled by setting eadc bit in ien1 register. this flag is set by hardware and must be reset by software. 21.2 registers table 31. adcon register adcon (s:f3h) ? adc control register reset value = 0000 0000b table 32. adclk register adclk (s:f2h) ? adc clock divider register reset value = 0000 0000b 76543210 - adidl aden adeoc adsst - - adcs bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6 adidl adc pseudo-idle mode set to suspend the cpu core activity (pseudo-idle mode) during conversion. clear by hardware at the end of conversion. 5aden adc enable bit set to enable the a to d converter. clear to disable the a to d converter and put it in low power stand by mode. 4adeoc end of conversion flag set by hardware when adc result is ready to be read. this flag can generate an interrupt. must be cleared by software. 3 adsst start and status bit set to start an a to d conversion on the selected channel. cleared by hardware at the end of conversion. 2 - 1 - reserved the value read from these bits is always 0. do not set these bits. 0 adcs channel selection bit set to select channel 0 for conversion. clear to select channel 1 for conversion. 76543210 - - - adcd4 adcd3 adcd2 adcd1 adcd0 bit number bit mnemonic description 7 - 5 - reserved the value read from these bits is always 0. do not set these bits. 4 - 0 adcd4:0 adc clock divider 5-bit divider for adc clock generation.
151 4173d?usb?02/06 at89c5132 table 33. addh register addh (s:f5h read only) ? adc data high byte register reset value = 0000 0000b table 34. addl register addl (s:f4h read only) ? adc data low byte register reset value = 0000 0000b 76543210 adat9 adat8 adat7 adat6 adat5 adat4 adat3 adat2 bit number bit mnemonic description 7 - 0 adat9:2 adc data 8 most significant bits of the 10-bit adc data. 76543210 ------adat1adat0 bit number bit mnemonic description 7 - 2 - reserved the value read from these bits is always 0. do not set these bits. 1 - 0 adat1:0 adc data 2 least significant bits of the 10-bit adc data.
152 4173d?usb?02/06 at89c5132 22. keyboard interface the at89c5132 implements a keyboard interface allowing the connection of a 4 x n matrix key - board. it is based on 4 inputs with programmabl e interrupt capability on both high or low level. these inputs are available as alternate function of p1.3:0 and allow exit from idle and power down modes. 22.1 description the keyboard interfaces with the c51 core through two special function registers: kbcon, the keyboard control register (see table 101 ); and kbsta, the keyboard c ontrol and status register (see table 102 ). the keyboard inputs are considered as 4 independent interrupt sources sharing the same inter - rupt vector. an interrupt enable bit (ekb in ien1 register) allows global enable or disable of the keyboard interrupt (see figure 22-1 ). as detailed in figure 22-2 each keyboard input has the capability to detect a programmable level according to kinl3:0 bit value in kbcon register. level detection is th en reported in in terrupt flags kinf3:0 in kbsta register. any of the kinf3:0 flags can trigger a keyboard interrupt. to do so, corresponding mask bits kinm3:0 in kbcon register must be cleared. the keyboard interrupt service routine is executed each time an unmasked kinfx flag is set. the interrupt must be acknowledged by reading kbsta which automatically clears kinf3:0 flags. this structure allows keyboard arrangement from 1 by n to 4 by n matrix and allow usage of kin inputs for any other purposes. figure 22-1. keyboard interface block diagram figure 22-2. keyboard input circuitry 22.1.1 power reduction mode kin3:0 inputs allow exit from idle and power down modes as detailed in section ?power man - agement?, page 44 . to enable this feature, kpde bit in kbsta register must be set to logic 1. due to the asynchronous keypad detection in power down mode (all clocks are stopped), exit may happen on parasitic key press. in this case , no key is detected and software must enter power-down again. 22.2 registers table 101. kbcon register kin0 keyboard interface interrupt request ekb ien1.4 input circuitry kin1 input circuitry kin2 input circuitry kin3 input circuitry kin3:0 kinm3:0 kbcon.3:0 kinf3:0 kbsta.3:0 kinl3:0 kbcon.7:4 0 1
153 4173d?usb?02/06 at89c5132 kbcon (s:a3h) ? keyboard control register reset value = 0000 1111b 22.2.0.1 table 102. kbsta register kbsta (s:a4h) ? keyboard co ntrol and status register reset value = 0000 0000b 76543210 kinl3 kinl2 kinl1 kinl0 kinm3 kinm2 kinm1 kinm0 bit number bit mnemonic description 7 - 4 kinl3:0 keyboard input level bit set to enable a high level detection on the respective kin3:0 input. clear to enable a low level detection on the respective kin3:0 input. 3 - 0 kinm3:0 keyboard input mask bit set to prevent the respective kinf3:0 fl ag from generating a keyboard interrupt. clear to allow the respective kinf3: 0 flag to generate a keyboard interrupt. 76543210 kpde - - - kinf3 kinf2 kinf1 kinf0 bit number bit mnemonic description 7kpde keyboard power down enable bit set to enable exit of power down mode by the keyboard interrupt. clear to disable exit of power down mode by the keyboard interrupt. 6 - 4 - reserved the values read from these bits are always 0. do not set these bits. 3 - 0 kinf3:0 keyboard input interrupt flag set by hardware when the respective kin3:0 input detects a programmed level. cleared when reading kbsta.
154 4173d?usb?02/06 at89c5132 23. electrical characteristics 23.1 absolute maximum ratings 23.2 dc characteristics 23.2.1 digital logic storage temperature ..................................... -65 c to +150 c voltage on any other pin to v ss ..................................... -0.3 to +4.0v i ol per i/o pin ................................................................. 5 ma power dissipation ............................................................. 1 w ambient temperature under bias.......... .......... -40 c to +85 c v dd ....................................................................................... 2.7v to 3.3v *notice: stressing the device beyond the ?absolute maxi- mum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 103. digital dc characteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c symbol parameter min typ (1) max units test conditions v il input low voltage -0.5 0.2v dd - 0.1 v v ih1 input high voltage (except rst, x1) 0.2v dd + 1.1 v dd v v ih2 input high voltage (rst, x1) 0.7v dd (2) v dd + 0.5 v v ol1 output low voltage (except p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 1.6 ma v ol2 output low voltage (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 3.2 ma v oh1 output high voltage (p1, p2, p3, p4 and p5) v dd - 0.7 v i oh = -30 a v oh2 output high voltage (p0, p2 address mode, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout, d+, d-) v dd - 0.7 v i oh = -3.2 ma i il logical 0 input current (p1, p2, p3, p4 and p5) -50 a vin = 0.45 v
155 4173d?usb?02/06 at89c5132 notes: 1. typical values are obtained using v dd = 3 v and t a = 25 c. they are not tested and there is no guarantee on these values. 2. flash retention is guaranteed with the same formula for v dd min down to 0v. 3. see table 154 for typical consumption in player mode. 23.2.2 i dd, i dl and i pd test conditions figure 23-1. i dd test condition, active mode i li input leakage current (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 10 a 0.45< v in < v dd i tl logical 1 to 0 transition current (p1, p2, p3, p4 and p5) -650 a vin = 2.0 v r rst pull-down resistor 50 90 200 k c io pin capacitance 10 pf t a = 25 c v ret v dd data retention limit 1.8 v i dd operating current (3) x1 / x2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i dl idle mode current (3) x1 / x2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i pd power-down mode current 20 500 av ret < v dd < 3.3 v table 103. digital dc characteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c symbol parameter min typ (1) max units test conditions rst tst p0 all other pins are unconnected vdd vdd vdd i dd vdd pvdd uvdd avdd x2 clock signal vss x1 (nc) vss pvss uvss avss
156 4173d?usb?02/06 at89c5132 figure 23-2. i dl test condition, idle mode figure 23-3. i pd test condition, power-down mode 23.2.3 a-to-d converter table 104. a-to-d converter dc characteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c x2 vdd clock signal rst vss tst x1 p0 (nc) i dl all other pins are unconnected vss vdd vss vdd pvdd uvdd avdd pvss uvss avss rst mcmd p0 all other pins are unconnected vss vdd tst mdat vdd i pd vdd pvdd uvdd avdd x2 vss x1 (nc) vss pvss uvss avss symbol parameter min typ max units test conditions av dd analog supply voltage 2.7 3.3 v ai dd analog operating supply current 600 a av dd = 3.3v ain1:0 = 0 to av dd ai pd analog standby current 2 a a v dd = 3.3v aden = 0 or pd = 1 av in analog input voltage av ss a v dd v av ref reference voltage a refn a refp av ss 2.4 a v dd v v r ref aref input resistance 10 30 k t a = 25 c c ia analog input capacitance 10 pf t a = 25 c
157 4173d?usb?02/06 at89c5132 23.2.4 oscillator and crystal 23.2.4.1 schematic figure 23-4. crystal connection note: for operation with most standard crystals, no external components are needed on x1 and x2. it may be necessary to add external capacitors on x1 and x2 to ground in special cases (max 10 pf). x1 and x2 may not be used to drive other circuits. 23.2.4.2 parameters table 105. oscillator and crystal characteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c 23.2.5 phase lock loop 23.2.5.1 schematic figure 23-5. pll filter connection vss x1 x2 q c1 c2 symbol parameter min typ max unit c x1 internal capacitance (x1 - v ss )10pf c x2 internal capacitance (x2 - v ss )10pf c l equivalent load capacitance (x1 - x2) 5 pf dl drive level 50 w f crystal frequency 20 mhz rs crystal series resistance 40 cs crystal shunt capacitance 6 pf vss filt r c1 c2 vss
158 4173d?usb?02/06 at89c5132 23.2.5.2 parameters table 106. pll filter ch aracteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c 23.2.6 usb connection 23.2.6.1 schematic figure 23-6. usb connection 23.2.6.2 parameters table 35. usb termination characteristics v dd = 3 to 3.3 v, t a = -40 to +85 c 23.2.7 in-system programming 23.2.7.1 schematic figure 23-7. isp pull-down connection 23.2.7.2 parameters table 107. isp pull-down characteristics v dd = 3 to 3.3v , t a = -40 to +85 c symbol parameter min typ max unit r filter resistor 100 c1 filter capacitance 1 10 nf c2 filter capacitance 2 2.2 nf d+ d- vbus gnd d+ d- vss to p o w e r r usb r usb vdd supply r fs symbol parameter min typ max unit r usb usb termination resistor 27 r fs usb full speed resistor 1.5 k vss isp r isp symbol parameter min typ max unit r isp isp pull-down resistor 2.2 k
159 4173d?usb?02/06 at89c5132 24.2 ac characteristics 24.2.1 external 8-bit bus cycles 24.2.1.1 definition of symbols table 108. external 8-bit bus cycles timing symbol definitions 24.2.1.2 timings test conditions: capacitive load on all pins = 50 pf. table 109. external 8-bit bus cycle ? data read ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c signals conditions a address h high d data in l low l ale v valid q data out x no longer valid rrd z floating wwr symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llrl ale low to rd low 3t clcl -30 1.5t clcl -30 ns t rlrh rd pulse width 6t clcl -25 3t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avdv address valid to valid data in 9t clcl -65 4.5t clcl -65 ns t avrl address valid to rd low 4t clcl -30 2t clcl -30 ns t rldv rd low to valid data 5t clcl -30 2.5t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz instruction float after rd high 2t clcl -25 t clcl -25 ns
160 4173d?usb?02/06 at89c5132 table 110. external 8-bit bus cycle ? data write ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c 24.2.1.3 waveforms figure 24-8. external 8-bit bus cycle ? data read waveforms symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh data valid to wr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns t avdv t llax t rhdx t rhdz t avll t avrl p2 p0 rd ale t lhll t rlrh data in a15:8 t rlaz t llrl t rhlh t rldv d7:0 a7:0
161 4173d?usb?02/06 at89c5132 figure 24-9. external 8-bit bus cycle ? data write waveforms 24.2.2 external ide 16-bit bus cycles 24.2.2.1 definition of symbols table 111. external ide 16-bit bus cycles timing symbol definitions 24.2.2.2 timings test conditions: capacitive load on all pins = 50 pf. t whlh t avwl t llax t whqx p2 p0 wr ale t lhll t wlwh a15:8 t avll t qvwh d7:0 data out t llwl a7:0 signals conditions a address h high d data in l low l ale v valid q data out x no longer valid rrd z floating wwr
162 4173d?usb?02/06 at89c5132 table 112. external ide 16-bit bus cycle ? data read ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c table 113. external ide 16-bit bus cycle ? data write ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llrl ale low to rd low 3t clcl -30 1.5t clcl -30 ns t rlrh rd pulse width 6t clcl -25 3t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avdv address valid to valid data in 9t clcl -65 4.5t clcl -65 ns t avrl address valid to rd low 4t clcl -30 2t clcl -30 ns t rldv rd low to valid data 5t clcl -30 2.5t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz instruction float after rd high 2t clcl -25 t clcl -25 ns symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh data valid to wr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns
163 4173d?usb?02/06 at89c5132 24.2.2.3 waveforms figure 24-10. external ide 16-bit bus cycle ? data read waveforms note: d15:8 is written in dat16h sfr. figure 24-11. external ide 16-bit bus cycle ? data write waveforms note: d15:8 is the content of dat16h sfr. 24.2.3 spi interface 24.2.3.1 definition of symbols table 114. spi interface timing symbol definitions t avdv t llax t rhdx t rhdz t avll t avrl p2 p0 rd ale t lhll t rlrh data in t rlaz t llrl t rhlh t rldv d7:0 a7:0 data in d15:81 a15:8 t whlh t avwl t llax t whqx p2 p0 wr ale t lhll t wlwh t avll t qvwh d7:0 data out t llwl a7:0 d15:81 data out a15:8 signals conditions cclock hhigh i data in l low o data out v valid x no longer valid z floating
164 4173d?usb?02/06 at89c5132 24.2.3.2 timings table 115. spi interface master ac timing v dd = 2.7 to 3.3v, t a = -40 to +85 c notes: 1. value of this parameter depends on software. 2. test conditions: capacitive load on all pins = 100 pf symbol parameter min max unit slave mode t chch clock period 8 t osc t chcx clock high time 3.2 t osc t clcx clock low time 3.2 t osc t slch , t slcl ss low to clock edge 200 ns t ivcl , t ivch input data valid to clock edge 100 ns t clix , t chix input data hold after clock edge 100 ns t clov, t chov output data valid after clock edge 100 ns t clox , t chox output data hold time after clock edge 0 ns t clsh , t chsh ss high after clock edge 0 ns t ivcl , t ivch input data valid to clock edge 100 ns t clix , t chix input data hold after clock edge 100 ns t slov ss low to output data valid 130 ns t shox output data hold after ss high 130 ns t shsl ss high to ss low (1) t ilih input rise time 2 s t ihil input fall time 2 s t oloh output rise time 100 ns t ohol output fall time 100 ns master mode t chch clock period 4 t osc t chcx clock high time 1.6 t osc t clcx clock low time 1.6 t osc t ivcl , t ivch input data valid to clock edge 50 ns t clix , t chix input data hold after clock edge 50 ns t clov, t chov output data valid after clock edge 65 ns t clox , t chox output data hold time after clock edge 0 ns t ilih input data rise time 2 s t ihil input data fall time 2 s t oloh output data rise time 50 ns t ohol output data fall time 50 ns
165 4173d?usb?02/06 at89c5132 24.2.3.3 waveforms figure 24-12. spi slave waveforms (sscpha = 0) note: 1. not defined but generally the msb of the character which has just been received. figure 24-13. spi slave waveforms (sscpha = 1) note: 1. not defined but generally the lsb of the character which has just been received. t slcl t slch t chcl t clch mosi (input) sck (sscpol = 0) (input) ss (input) sck (sscpol = 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov 1 t shox t shsl t chsh t clsh si (input) sck (sscpol = 0) (output) ss 1 (output) sck (sscpol = 1) (output) so (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
166 4173d?usb?02/06 at89c5132 figure 24-14. spi master waveforms (sscpha = 0) note: 1. ss handled by software using general purpose port pin. figure 24-15. spi master waveforms (sscpha = 1) note: 1. ss handled by software using general purpose port pin. 24.2.4 two-wire interface 24.2.4.1 timings table 36. twi interface ac timing t chcl t clch mosi (input) sck (sscpol = 0) (input) ss 1 (input) sck (sscpol = 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t clov t chov t clox t chox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov 1 t shox t shsl t chsh t clsh t slcl t slch si (input) sck (sscpol = 0) (output) ss 1 (output) sck (sscpol = 1) (output) so (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
167 4173d?usb?02/06 at89c5132 v dd = 2.7 to 3.3 v, t a = -40 to +85 c notes: 1. at 100 kbit/s. at other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. spikes on the sda and scl lines with a duration of less than 3t clcl will be filtered out. maxi - mum capacitance on bus-lines sda and scl= 400 pf. 4. t clcl = t osc = one oscillator clock period. 24.2.4.2 waveforms figure 24-16. two wire waveforms symbol parameter input min max output min max t hd ; sta start condition hold time 14t clcl (4) 4.0 s (1) t low scl low time 16t clcl (4) 4.7 s (1) t high scl high time 14t clcl (4) 4.0 s (1) t rc scl rise time 1 s- (2) t fc scl fall time 0.3 s0.3 s (3) t su ; dat1 data set-up time 250 ns 20t clcl (4) - t rd t su ; dat2 sda set-up time (before repeated start condition) 250 ns 1 s (1) t su ; dat3 sda set-up time (before stop condition) 250 ns 8t clcl (4) t hd ; dat data hold time 0 ns 8t clcl (4) - t fc t su ; sta repeated start set-up time 14t clcl (4) 4.7 s (1) t su ; sto stop condition set-up time 14t clcl (4) 4.0 s (1) t buf bus free time 14t clcl (4) 4.7 s (1) t rd sda rise time 1 s - (2) t fd sda fall time 0.3 s0.3 s (3) ts u ; d at 1 t su ;sta ts u ; d at 2 t hd ;sta t high t low sda (input/output) 0.3 v dd 0.7 v dd t buf t su ;sto 0.7 v dd 0.3 v dd t rd t fd t rc t fc scl (input/output) t hd; dat t su; dat3 start or repeated start condition start condition stop condition repeated start condition
168 4173d?usb?02/06 at89c5132 24.2.5 mmc interface 24.2.5.1 definition of symbols table 116. mmc interface timing symbol definitions 24.2.5.2 timings table 117. mmc interface ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c, cl 100pf (10 cards) 24.2.5.3 waveforms figure 24-17. mmc input output waveforms signals conditions cclock hhigh d data in l low o data out v valid x no longer valid symbol parameter min max unit t chch clock period 50 ns t chcx clock high time 10 ns t clcx clock low time 10 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t dvch input data valid to clock high 3 ns t chdx input data hold after clock high 3 ns t chox output data hold after clock high 5 ns t ovch output data valid to clock high 5 ns t ivch mclk mdat input t chch t clcx t chcx t chcl t clch mcmd input t chix t ovch mdat output mcmd output t chox
169 4173d?usb?02/06 at89c5132 24.2.6 audio interface 24.2.6.1 definition of symbols table 118. audio interface timing symbol definitions 24.2.6.2 timings table 119. audio interface ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c, cl 30pf note: 32-bit format with fs = 48 khz. 24.2.6.3 waveforms figure 24-18. audio interface waveforms signals conditions cclock hhigh o data out l low s data select v valid x no longer valid symbol parameter min max unit t chch clock period 325.5 (1) ns t chcx clock high time 30 ns t clcx clock low time 30 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t clsv clock low to select valid 10 ns t clov clock low to data valid 10 ns dclk t chch t clcx t chcx t clch t chcl dsel ddat right left t clsv t clov
170 4173d?usb?02/06 at89c5132 24.2.7 analog to digital converter 24.2.7.1 definition of symbols table 120. analog to digital converter timing symbol definitions 24.2.7.2 characteristics table 37. analog to digital converter ac characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c notes: 1. av dd = av refp = 3.0 v, av ss = av refn = 0 v. adc is monotonic with no missing code. 2. the differential non-linearity is the differenc e between the actual step width and the ideal step width (see figure 24-20 ). 3. the integral non-linearity is the peak difference between the center of th e actual step and the ideal transfer curve after appropriate adj ustment of gain and offset errors (see figure 24-20 ). 4. the offset error is the absolute difference betw een the straight line whic h fits the actual trans - fer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see figure 24-20 ). 5. the gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), an d the straight line which fits the ideal transfer curve (see figure 24-20 ). signals conditions cclock hhigh e enable (aden bit) l low s start conversion (adsst bit) symbol parameter min max unit t clcl clock period 4 s t ehsh start-up time 4 s t shsl conversion time 11t clcl s dle differential non- linearity error (1)(2) 1lsb ile integral non-linearity errorss (1)(3) 2lsb ose offset error (1)(4) 4lsb ge gain error (1)(5) 4lsb
171 4173d?usb?02/06 at89c5132 24.2.7.3 waveforms figure 24-19. analog-to-digital converter internal waveforms figure 24-20. analog-to-digital converter characteristics aden bit adsst bit t ehsh t shsl clk t clcl 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 offset error code out avin (lsbideal) ose offset error ose gain error ge ideal transfer curve 1 lsb (ideal) integral non-linearity (ile) differential non-linearity (dle) center of a step example of an actual transfer curve 0 0
172 4173d?usb?02/06 at89c5132 24.2.8 flash memory 24.2.8.1 definition of symbols table 121. flash memory timing symbol definitions 24.2.8.2 timings table 122. flash memory ac timing v dd = 2.7 to 3.3v, t a = -40 to +85 c 24.2.8.3 waveforms figure 24-21. flash memory ? isp waveforms note: 1. isp must be driven through a pull-down resistor (see section ?in-system programming?, page 158 ). figure 24-22. flash memory ? internal busy waveforms 24.2.9 external clock drive and logic level references 24.2.9.1 definition of symbols table 123. external clock timing symbol definitions signals conditions sisp l low r rst v valid b fbusy flag x no longer valid symbol parameter min typ max unit t svrl input isp valid to rst edge 50 ns t rlsx input isp hold after rst edge 50 ns t bhbl flash internal busy (programming) time 10 ms n fcy number of flash write cycles 100k cycle t fdr flash data retention time 10 year rst t svrl isp (1) t rlsx fbusy bit t bhbl signals conditions cclock hhigh l low x no longer valid
173 4173d?usb?02/06 at89c5132 24.2.9.2 timings table 124. external clock ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c 24.2.9.3 waveforms figure 24-23. external clock waveform figure 24-24. ac testing input/output waveforms notes: 1. during ac testing, all inputs are driven at v dd -0.5v for a logic 1 and 0.45v for a logic 0. 2. timing measurements are made on all outputs at v ih min for a logic 1 and v il max for a logic 0. figure 24-25. float waveforms note: for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float wh en a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh = 20 ma. symbol parameter min max unit t clcl clock period 50 ns t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns t cr cyclic ratio in x2 mode 40 60 % 0.45 v t clcl v dd - 0.5 v ih1 v il t chcx t clch t chcl t clcx 0.45 v v dd - 0.5 0.7 v dd 0.3 v dd v ih min v il max inputs outputs v load v oh - 0.1v v ol + 0.1v v load + 0.1v v load - 0.1v timing reference points
174 4173d?usb?02/06 at89c5132 25. ordering information note: 1. plcc84 package only available for development board. possible order entries (1) part number memory size (bytes) supply voltage temperature range max frequency (mhz) package packing product marking AT89C5132-ROTIL 64k flash 3v industrial 40 tqfp80 tray 895132-il at89c5132-rotul 64k flash 3v industrial & green 40 tqfp80 tray 895132-ul
175 4173d?usb?02/06 at89c5132 26. package information 26.1 tqfp80
176 4173d?usb?02/06 at89c5132 26.2 plcc84
177 4173d?usb?02/06 at89c5132 27. datasheet revision history for at89c5132 27.1 changes from 4173a -08/02 to 4173b-03/04 1. suppression of rom product version. 2. suppression of tqfp64 package. 27.2 changes from 4173b -03/04 - 4173c - 07/04 1. add usb connection schematic in usb section. 2. add usb termination characteristic s in dc characteristics section. 3. page access mode clarification in data memory section. 27.3 changes from 4173c -07/04 - 4173d - 01/05 1. interrupt priority number clarification to match number defined by development tools. 27.4 changes from to 4317d - 01/05 to 4173e - 02/06 1. added green product ordering information.
i 4173d?usb?02/06 at89c5132 1 description ............ .............. .............. ............... .............. .............. ............ 1 2 typical applications ......... ................ ............... .............. .............. ............ 1 3 block diagram ............ ................ ................. ................ ................. ............ 2 4 pin description ......... ................ ................ ................. ................ ............... 3 4.1 signals ................................................................................................................... ...4 4.2 internal pin structure ..............................................................................................10 5 address spaces ........... ................. ................ ................. .............. .......... 11 6 clock controller ....... ................ ................ ................. ................ ............. 12 6.1 oscillator ................................................................................................................ 12 6.2 x2 feature ..............................................................................................................12 6.3 pll ....................................................................................................................... ..13 6.4 registers ................................................................................................................1 4 7 program/code memory ......... .............. .............. .............. .............. ........ 17 7.1 flash memory architecture .................... ................................................................17 7.2 hardware security system .....................................................................................18 7.3 boot memory execution .........................................................................................19 7.4 registers ................................................................................................................2 0 7.5 hardware bytes ......................................................................................................20 8 data memory ............ ................ ................ ................. ................ ............. 22 8.1 internal space ........................................................................................................22 8.2 external space .......................................................................................................23 8.3 dual data pointer ...................................................................................................26 8.4 registers ................................................................................................................2 7 9 special function registers ... .............. .............. .............. .............. ........ 29 10 interrupt system ............. ................ ................. .............. .............. .......... 34 10.1 interrupt system priorities ....................................................................................34 10.2 external interrupts .. ..............................................................................................37 10.3 registers ..............................................................................................................38 11 power management ............ .............. ............... .............. .............. .......... 44 11.1 reset .................................................................................................................... 44 11.2 reset recommendation to prevent flash corruption ..........................................45 11.3 idle mode ..............................................................................................................46 11.4 power-down mode ...............................................................................................46
ii 4173d?usb?02/06 at89c5132 11.5 registers ..............................................................................................................48 12 timers/counters ............... ................ ............... .............. .............. .......... 49 12.1 timer/counter operations ....................................................................................49 12.2 timer clock controller ..........................................................................................49 12.3 timer 0 .................................................................................................................5 0 12.4 timer 1 .................................................................................................................5 2 12.5 interrupt ................................................................................................................ 53 12.6 registers ..............................................................................................................54 13 watchdog timer ........... ................. ................ ................. .............. .......... 57 13.1 description ...........................................................................................................57 13.2 watchdog clock controller ...................................................................................57 13.3 watchdog operation ............................................................................................58 13.4 registers ..............................................................................................................59 14 audio output interface ....... .............. ............... .............. .............. .......... 60 14.1 description ...........................................................................................................60 14.2 clock generator ...................................................................................................60 14.3 data converter .....................................................................................................61 14.4 audio buffer ..........................................................................................................62 14.5 interrupt request ..................................................................................................63 14.6 voice or sound playing ........................................................................................63 14.7 registers ..............................................................................................................64 15 universal serial bus ......... ................ ............... .............. .............. .......... 67 15.1 description ...........................................................................................................68 15.2 usb interrupt system ...........................................................................................70 15.3 registers ..............................................................................................................72 16 multimedia card controller .............. ............... .............. .............. .......... 82 16.1 card concept .......................................................................................................82 16.2 bus concept .........................................................................................................82 16.3 description ...........................................................................................................87 16.4 clock generator ...................................................................................................88 16.5 command line controller ....................................................................................88 16.6 data line controller .............................................................................................90 16.7 interrupt ................................................................................................................ 96 16.8 registers ..............................................................................................................97
iii 4173d?usb?02/06 at89c5132 17 ide/atapi interface .......... .............. .............. .............. .............. ........... 104 17.1 description .........................................................................................................104 17.2 registers ............................................................................................................106 18 serial i/o port ...... .............. .............. .............. .............. .............. ........... 107 18.1 mode selection ...................................................................................................107 18.2 baud rate generator .........................................................................................107 18.3 synchronous mode (mode 0) .............................................................................108 18.4 asynchronous modes (modes 1, 2 and 3) ..........................................................111 18.5 multiprocessor communic ation (modes 2 and 3) ...............................................114 18.6 automatic address recogn ition .........................................................................114 18.7 interrupt ..............................................................................................................11 6 18.8 registers ............................................................................................................116 19 synchronous peripheral interface ............ ................ .............. ........... 120 19.1 description .........................................................................................................121 19.2 interrupt ..............................................................................................................12 4 19.3 configuration ......................................................................................................124 19.4 registers ............................................................................................................129 20 two-wire interface (twi) controller ..... ................. ................ ............. 131 20.1 description .........................................................................................................131 20.2 registers ............................................................................................................145 21 analog to digital converter ............. ............... .............. .............. ........ 147 21.1 description .........................................................................................................147 21.2 registers ............................................................................................................150 22 keyboard interface ........... .............. .............. .............. .............. ........... 152 22.1 description .........................................................................................................152 22.2 registers ............................................................................................................152 23 electrical characteristics ... .............. ............... .............. .............. ........ 154 23.1 absolute maximum ratings ................................................................................154 23.2 dc characteristics .............................................................................................154 23.3 ac characteristics ..............................................................................................159 24 ordering information .......... .............. ............... .............. .............. ........ 174 25 package information ........... .............. ............... .............. .............. ........ 175 25.1 tqfp80 .............................................................................................................175
iv 4173d?usb?02/06 at89c5132 25.2 plcc84 ..............................................................................................................176 26 datasheet change log for at89c5132 ..... ................ .............. ........... 176 26.1 changes from 4173a-08/02 to 4173b-03/04 ......................................................176 26.2 changes from 4173b-03/04 - 4173c - 07/04 .....................................................176 26.3 changes from 4173c-07/04 - 4173d - 01/05 .....................................................177 26.4 changes from 4173d - 01/05 - 4173e - 02/06 ...................................................177

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